k4d261638e Samsung Semiconductor, Inc., k4d261638e Datasheet
k4d261638e
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k4d261638e Summary of contents
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... K4D261638E 128Mbit DDR SDRAM Double Data Rate Synchronous DRAM Samsung Electronics reserves the right to change products or specification without notice 16Bit x 4 Banks Revision 1.2 July 2003 - 1 - 128M DDR SDRAM Rev. 1.2 (Jul. 2003) ...
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... Changed tRC of K4D261638E-TC33/36 from 13tCK to 15tCK • Changed tRFC of K4D261638E-TC33/36 from 15tCK to 17tCK • Changed tRAS of K4D261638E-TC33/36 from 9tCK to 10tCK • Changed tRP of K4D261638E-TC33/36 from 4tCK to 5tCK • Changed tDAL of K4D261638E-TC33/36 from 7tCK to 8tCK Revision 0.3 (December 3, 2002) - • Typo corrected Revision 0.2 (November 12, 2002) - • ...
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... GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM The K4D261638E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 2,097,152 words by 16 bits, fabricated with SAMSUNG extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications ...
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... K4D261638E PIN CONFIGURATION (Top View) PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use DDQ ...
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... K4D261638E INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF NC/RFU No connection/ Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK ...
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... K4D261638E BLOCK DIAGRAM (2Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 2Mx16 2Mx16 2Mx16 2Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D261638E FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D261638E MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D261638E EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... IH DDQ 5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate For any pin under test input of 0V < For the K4D261638E-TC2A, VDD & VDDQ = 2.8V+0.1V Symbol OUT V ...
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... Clock Input Crossing Point Voltage; CK and CK Note : the magnitude of the difference between the input level on CK and the input level The value expected to equal 0.5 For the K4D261638E-TC2A, VDD & VDDQ = 2.8V+0.1V Test Condition - Burst Lenth=2 ...
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... CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition 1.For the K4D261638E-TC2A, VDD & VDDQ = 2.8V+0.1V. Output CAPACITANCE (V =2.5V Parameter Input capacitance( CK Input capacitance ...
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... K4D261638E AC CHARACTERISTICS Sym- Parameter bol CL cycle time CK CL high level width low level width CL t DQS out access time from CK DQSCK t Output access time from Data strobe edge to Dout edge DQSQ t Read preamble RPRE t Read postamble RPST valid DQS-in ...
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... Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D261638E-TC2A Frequency Cas Latency 350MHz ( 2.86ns ) 4 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D261638E-TC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 -2A -33 Min Max ...
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... Cas Latency 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D261638E-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D261638E-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 Simplified Timing @ BL CK ...
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... K4D261638E PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× 128M DDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev. 1.2 (Jul. 2003) ...