k4h510438c-uc/lb3 Samsung Semiconductor, Inc., k4h510438c-uc/lb3 Datasheet - Page 16

• Manufacturer Part Number: k4h510438c-uc/lb3
• Description: 512mb C-die Ddr Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

19.0 AC Timming Parameters & Specifications
DDR SDRAM 512Mb C-die (x4, x8, x16)
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Power Down Exit Time
Parameter
CL=2.0
CL=2.5
CL=3.0
tWPRES
tDQSCK
Symbol
tDQSQ
tWPRE
tRPRE
tDQSS
tDQSH
tXSNR
tXSRD
tWPST
tRPST
tDQSL
tDIPW
tPDEX
tRCD
tRRD
tWTR
tMRD
tREFI
tQHS
tRFC
tRAS
tDSS
tDSH
tRAP
tIPW
tDAL
tWR
tRC
tCH
tDS
tDH
tQH
tHP
tRP
tCK
tCL
tAC
tHZ
tLZ
tIS
tIH
tIS
tIH
or tCHmin
(tWR/tCK)
(DDR400@CL=3.0)
(tRP/tCK)
tCLmin
-0.55
-0.65
-0.65
-0.65
-tQHS
Min
0.45
0.45
0.72
0.25
0.35
0.35
1.75
200
0.9
0.4
0.2
0.2
0.6
0.6
0.7
0.7
0.4
0.4
2.2
tHP
0.4
55
70
40
15
15
10
15
10
75
15
2
6
5
0
+
1
-
-
CC
+0.55
+0.65
+0.65
+0.65
Max
1.28
0.55
0.55
70K
0.4
1.1
0.6
7.8
0.5
0.6
12
10
-
-
-
(tWR/tCK)
(DDR333@CL=2.5)
or tCHmin
(tRP/tCK)
tCLmin
-tQHS
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.45
0.45
1.75
-0.6
-0.7
-0.7
-0.7
200
7.5
0.9
0.4
0.2
0.2
0.8
0.8
2.2
tHP
0.4
60
72
42
18
18
12
15
12
75
18
1
6
0
+
1
-
-
B3
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
0.55
70K
1.1
0.6
7.8
0.6
12
12
-
-
-
or tCHmin
(tWR/tCK)
(DDR266@CL=2.0)
(tRP/tCK)
tCLmin
-0.75
-0.75
-0.75
-0.75
-tQHS
0.45
0.45
0.75
0.25
0.35
0.35
1.75
Min
200
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
1.0
1.0
0.5
0.5
2.2
tHP
0.4
65
75
45
20
20
15
15
15
75
20
1
0
+
1
-
-
A2
+0.75
+0.75
+0.75
+0.75
Max
0.55
0.55
1.25
0.75
70K
0.5
1.1
0.6
7.8
0.6
12
12
-
-
-
Rev. 1.2 January 2007
or tCHmin
(tWR/tCK)
(DDR266@CL=2.5) Unit
(tRP/tCK)
tCLmin
-0.75
-0.75
-0.75
-0.75
-tQHS
Min
0.45
0.45
0.75
0.25
0.35
0.35
1.75
200
7.5
0.4
0.2
0.2
0.9
0.9
1.0
0.5
0.5
2.2
0.4
0.9
1.0
tHP
65
75
45
20
20
15
15
10
15
75
20
1
0
+
1
-
-
DDR SDRAM
B0
+0.75
+0.75
+0.75
+0.75
Max
0.55
0.55
1.25
0.75
70K
0.5
1.1
0.6
7.8
0.6
12
12
-
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
15, 17~19
15, 17~19
16~19
16~19
20, 21
Note
j, k
j, k
22
13
11
11
18
18
14
21
21
12
23