k4h560838f-uccc ETC-unknow, k4h560838f-uccc Datasheet - Page 10

• Manufacturer Part Number: k4h560838f-uccc
• Description: Ddr Sdram Ddr Sdram 256mb F-die X8, X16
• Manufacturer: ETC-unknow

Input/Output Capacitance
DDR SDRAM 256Mb F-die (x8, x16)
DDR SDRAM Spec Items & Test Conditions
Note :
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles; CS = high between valid commands.
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition; CS = high between valid commands.
Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns for
DDR400; Vin = Vref for DQ,DQS and DM.
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;
Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5ns
DDR400; Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m
A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DM
and DQS inputs changing twice per clock cycle, 50% of input data changing at every transfer
Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns;
Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400.
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
Input capacitance( CK, CK )
Data & DQS input/output capacitance
Input capacitance(DM for 8, UDM/LDM for x16)
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
3. Unused pins are tied to ground.
4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25°C, Vout(dc) =
(to facilitate trace matching at the board level).
This is required to match signal propagation times of DQ, DQS, and DM in the system.
VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading
Parameter
Conditions
Symbol
COUT
CIN1
CIN2
CIN3
Min
2
2
4
4
(V
Max
3
3
5
5
DD
=2.6, V
Rev. 1.1 August. 2003
DDQ
Delta
0.25
0.5
0.5
=2.6V, T
DDR SDRAM
A
= 25°C, f=1MHz)
Unit
pF
pF
pF
pF
Symbol
IDD4W
IDD2Q
IDD3N
IDD4R
IDD2P
IDD2F
IDD3P
IDD0
IDD1
IDD5
IDD6
1,2,3,4
1,2,3,4
Note
4
4