srf-2724cs RF Micro Devices, srf-2724cs Datasheet
srf-2724cs
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srf-2724cs Summary of contents
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... CTX Functional Block Diagram Product Description The SRF-2724CS is a fully integrated 1.5Mbps frequency shift keyed (FSK) trans- ceiver that operates in the unlicensed 2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone application and includes all the fre- quency generation, receive, and transmit functions ...
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... SRF-2724CS Absolute Maximum Ratings Parameter VCCA, VDD Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Normal Temperature Range VCCA Range VDD Range Thermal Resistance Parameter Min. Power Consumption Analog Supply (VCCA) 2.7 Digital Supply Voltage 2.7 Bandgap Voltage Supply current, STANDBY Mode ...
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... dBm 3 6 dBm Ω SRF-2724CS Condition VCCA=VDD=3.3V, T =25°C, f =6.144MHz, A REF Data Rate=1.536Mbps, 13kHz Loop Filter as shown in Figure 1 f =2445MHz C f =2445MHz C FSK modulation, f =±512kHz DEV <12.5% CER at 1.536Mchip/s <0.1% BER at 1.536Mbps 3dB Bandwidth <12.5% CER at 1.536Mchip/s < ...
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... SRF-2724CS Parameter Min. Transmit Modulation Modulation Deviation at 2.4GHz 500 Modulation center frequency off- -50 set Transmit Data Filter Transmit Data Filter Bandwidth TX spurious TX spurious image Interface Logic Levels Input (DIN, XCEN, RXON, DATA, CLK, EN) Input high voltage 0.75*VDD Input low voltage 0 Input bias current ...
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... VCCA supply and greater than 2.7V. A capacitor must be tied between this pin and ground to decouple (bypass) noise. 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Power and Ground SRF-2724CS Interface Schematic See Pin 11 below. VCCA 24 0.7V ...
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... SRF-2724CS Pin Function Description 17 RX1 Receive RF Input. Nominal impedance at 2445MHz is 2.6-j2.6 with a sim- ple matching network required for optimum noise figure. This input con- nects to the base of an NPN transistor and should be AC coupled. 21 TXO TX RF open-collector output. This output requires a DC path to VCCA. ...
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... An AC-coupled sine or square wave source drives this self-biased input. 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Data, cont. Mode Control and Interface Lines SRF-2724CS Interface Schematic VDD 31 250 Ω 32 DOUT VSS ...
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... SRF-2724CS Pin Function Description 11 QPO Charge Pump Output of the phase detector. This is connected to the exter- nal PLL loop filter. 15 VTUNE VCO Tuning Voltage input from the PLL loop filter. This pin is very sensitive to noise coupling and leakage currents. 26 VBG Bandgap Decouple Voltage. Decoupled to ground with 220nF capacitor. ...
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... Serial control bus data is clocked in on the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS. 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Serial Bus Signals, cont. SRF-2724CS Interface Schematic VDD ...
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... SRF-2724CS X CEN RXON PAON EN DATA CLK AOUT V SS ANTENNA T/R SWITCH PA Figure 1: Typical SRF-274CS Application Diagram 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Proposed Pin Diagram ...
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... VCO resonator. In RECEIVE MODE, the SRF-2724CS is a dual conversion Low IF receiver. No external SAW filters are required. The integrated image reject mixer gives sufficient rejection in this channel. All channel filtering and demodulation is performed using active fil- ters, which are automatically aligned ...
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... The SRF-2724CS is intended for use in TDD and TDMA radios in battery-powered equipment. To minimize power consumption it is designed to switch rapidly from a low power mode (STANDBY active mode. The SRF-2724CS can also make a quick transition from receive to transmit for TDD operation. Prior to transmitting or receiving, time should be allowed for the PLL to lock and for the filters to align ...
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... Low IF filter, hard limiter, frequency to voltage converter, and data filter to the AOUT pin and data slicer where the digital NRZ data is available at the DOUT pin. A 20dB step AGC extends the dynamic range of the receiver. The SRF-2724CS receive chain is a Low IF receiver using advanced integrated radio techniques to eliminate external IF filters and minimize external RF filter requirements ...
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... SRF-2724CS PLL Programming and Channel Selection The SRF-2724CS PLL is programmed via control register 2 to the set RF center frequency of operation of the radio. The PLL does not need to be (though it can be) reprogrammed between RECEIVE and TRANSMIT modes. Nominal channel separation is 2.048MHz, allowing for over 40 non-overlapping channels in any given location. With careful planning, channels can be pro- grammed in 1024kHz steps as long as care is exercised to insure that two radio links will not share spectrum at any one time ...
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... Figure 4: Serial Bus Timing for Address and Data Programming 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. MIN TYP 50 100 DATA SRF-2724CS MAX Unit ...
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... A 3-wire serial data input bus sets the SRF-2724CS’s transceiver parameters and programs the PLL circuits. Entering 16-bit words into the SRF-2724CS serial interface performs programming. Three 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. The contents of these registers cannot be read back via this bus ...
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... PLL Charge Pump Polarity MSB Address Bit LSB Address Bit Description MSB Address Bit LSB Address Bit SRF-2724CS Definition Set all bits to 0 (zero) 0: RSSI clipped to 1.9V at -15dBm 1: RSSI not clipped 0: PAON Undisturbed Set Output always on TX mode ...
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... SRF-2724CS Table 5: Register 2 - Test Mode Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DTM2 DTM1 DTM0 ATM2 ATM1 ATM0 ADR1 ADR0 Power-On State On Power up, all register bits are cleared to the default value of 0 (zero). Power up is defined as occurring when VDD >2.0V. ...
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... Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. FREF XTAL Freq 9 6.144MHz 18 12.288MHz AOUT AOUT Pin Function 0 Transmit Power Control 1 Data Filter Analog Output TXCW Transmit Modulation 0 FSK Modulation Modulation SRF-2724CS PLL REF Freq 682.67kHz 682.67kHz ...
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... SRF-2724CS TPC - Register 0, Bit 7 Transmit Power Control: When the AOUT bit is low, this bit controls the state of the open-drain output pin. Although this bit can be changed at any time, the AOUT pin only changes state at the falling edge of RXON (see Table 10). ...
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... Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical Prelim DS090410 support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. RCLP RSSI Behavior 0 RSSI output clipped to a maximum of ~1.9V at -15dBm 1 RSSI output not clipped B13 to B2 CHQ - PLL Divide Ratio B13 to B2 CHQ - PLL Divide Ratio SRF-2724CS ...
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... SRF-2724CS ATM <2:0> - Register 2, Bits 2-4 Analog Test Mode: The test mode selected is described in Table 15. The performance of the SRF-2724CS is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is ATM<2:0>=<0,0,0>. When a non-zero value is written to the field, the RSSI and AOUT pins become analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. During normal operation, ATM< ...
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... FSK data takes its timing from the input data. In the receive chain, FSK demodulation, data filtering, and data slicing take place in the SRF-2724CS, and the digital data is output on the DOUT pin. Bit and word rate timing recovery are performed off chip. The data filter output is available on the AOUT pin for use with an optional external data slicer. ...
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... SRF-2724CS Table 17: Power Amplifier Timing Symbol Interface: RXI and TXO/TXOB The RXI receive input (pin 17) and the TXO/TXOB differential transmit outputs (pins 21 and 22) are the only RF I/O pins. The RXI pin requires a simple impedance matching network for optimum input noise figure. The TXO/TXOB pins require a matching network for maximum power output into the RF power amp ...
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... R AD20 50 1. .166 1.187 1 .209 R AD20 51 1. .160 1.181 1 .203 1.4 1.6 1.8 2 Figure 12: VCO Tuning Voltage versus Frequency SRF-2724CS RAD2006 @ +25°C Expanded Output Match 2.7V 3.3V 4.5V 2434.60 2451.40 2468.20 2485.00 MHz Vtun e vs. Freq uency +25° 160 4 1611 1 618 ...
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... SRF-2724CS PHYSICAL DIMENSIONS (INCHES/MILIMETERS 0.03 2 BSC (0 .8 BSC) Note: This package meets “Green” Pb-Free requirements and is compliant with the European Union directives WEEE (Waste Electrical and Electronic Equipment) and RoHS (Restriction of the use of certain Hazardous Substances in electrical and elec- tronic equipment). The package pins are finished with 100% matte tin. ...