am53c94 Advanced Micro Devices, am53c94 Datasheet - Page 17

• Manufacturer Part Number: am53c94
• Description: High Performance Scsi Controller
• Manufacturer: Advanced Micro Devices

Current Transfer Count Register
(00H–01H) Read Only
CTCREG – Bits 15:0 – CRVL 15:0 – Current
Value 15:0
This is a two-byte register. It counts down to keep track
of the number of DMA transfers. Reading this registers
will return the current value of the counter. The counter
will decrement by one for every byte transferred and two
for every word transferred over the SCSI bus. The trans-
action is complete when the count reaches zero. These
registers are automatically loaded with the values in the
Start Transfer Count Register every time a DMA com-
mand is issued.
In the target mode, this counter is decremented by the
active edge of DACK during the Data-In phase and by
REQC during the Data-Out phase.
In the initiator mode, the counter is decremented by the
active edge of DACK during the Synchronous Data-In
phase or by ACKC during the Asynchronous Data-In
phase and by DACK during the Data-Out phase.
Start Transfer Count Register (00H–01H)
Write Only
Current Transfer Count Register
CTCREG
Start Transfer Count Register
STCREG
CRVL15 CRVL14
STVL15 STVL14 STVL13 STVL12 STVL11 STVL10
CRVL7
STVL7
15
15
7
x
7
x
x
x
STVL6
CRVL6
14
14
6
x
6
x
x
x
CRVL13
STVL5
CRVL5
13
13
x
5
x
5
x
x
CRVL12 CRVL11 CRVL10
CRVL4
STVL4
12
12
4
x
x
x
4
x
STVL3
CRVL3
11
3
x
11
x
x
3
x
STVL2
CRVL2
10
x
2
x
10
2
x
x
Address: 00
Address: 00
STVL9
STVL1
CRVL9
CRVL1
9
x
1
x
9
1
16506C-017
x
x
16506C-16
Type: Write
Type: Read
P R E L I M I N A R Y
STVL8
STVL0
Am53C94/Am53C96
CRVL8
CRVL0
8
0
x
x
H–
H–
8
0
x
x
01
01
H
H
STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0
This is a two-byte register. It contains the number of
bytes to be transferred during a DMA operation. The
value of this register is set to the number of bytes to be
transferred prior to a DMA transfer command. This reg-
ister retains its programmed value until it is overwritten
and is not affected by hardware or software reset.
Therefore, it is not necessary to reprogram the count for
subsequent DMA transfers of the same size. Writing a
zero to this register sets a maximum transfer count of
65536 bytes. The value in this register is undefined at
power-up.
FIFO Register (02H) Read/Write
FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0
The bottom of the 16x9 FIFO is mapped into the FIFO
Register address. By reading and writing this register
the bottom of the FIFO can be read or written. This is the
only register that can also be accessed by DACK along
with DMARD or DMAWR. This register is reset to zero
by hardware or software reset and also at the start of a
selection or reselection sequence.
Command Register (03H) Read/Write
Command Register
CMDREG
Commands to the device are issued by writing to this
register. This register is two deep which allows for com-
mand queuing. The second command can be issued be-
fore the first one is completed. The Reset command and
the Stop DMA command are not queued and are exe-
cuted immediately. Reading this register will return the
command currently being executed (or the last com-
mand executed if there are no pending commands).
FIFO Register
FFREG
DMA
7
x
FF7
7
0
CMD6
6
x
FF6
6
0
CMD5
5
x
FF5
5
0
CMD4
FF4
4
x
4
0
CMD3
FF3
3
3
0
x
CMD2
FF2
2
0
2
x
Type: Read/Write
Type: Read/Write
CMD1
FF1
Address: 02
1
0
1
x
Address: 03
Command 6:0
Direct Memory
Access
16506C-019
16506C-18
AMD
FF0
0
0
CMD0
0
x
H
17
H