ppc405ex Applied Micro Circuits Corporation (AMCC), ppc405ex Datasheet - Page 12

• Manufacturer Part Number: ppc405ex
• Description: Powerpc 405ex Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PPC405EX – PowerPC 405EX Embedded Processor
PCI Express
The PCI Express single-lane interfaces include the following features:
Features include:
Security Function (optional)
The optional built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and
interrupt controllers.
Features include:
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• Compliant with PCI Express base specification 1.1
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
• PCI-Express to PCI-Express opaque (Non-Transparent) bridge
• Power Management
• Supports one virtual channel (VC0) with no Traffic Class (TC) filtering
• Maximum Payload block size 256B
• Supports up to 512B maximum Read request size
• Requests supported:
• Buffering in each PCI Express Port for the following transaction types:
• Parity checking on each buffer
• Programmable Outbound Memory (POM) Regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal
• Programmable Inbound Memory (PIM) Regions: 4 memory, 1 I/O, 1 expansion ROM
• INTx Interrupts support (PCI legacy):
• MSI - Message Signaled Interrupts
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP)
• Internet Protocol Security (IPSec) features
• Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS)
register
– Applications compliant with MSI rules are limited to one End Point port per PPC405EX
– Up to two posted outbound Write requests (memory and messages)
– Up to two posted inbound Write requests
– Up to two outbound Read requests outstanding on PCI Express
– Up to two inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express End Point
– 1KB Replay buffer: up to eight in flight transactions
– 512B for Outbound posted Writes
– 512B for Outbound Reads completion
– 512B for Inbound posted Writes
– 512B for Inbound Reads completion
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types Generation for Endpoints
– MSI Generation for End Point
– MSI Termination for Root Ports
– MSI_X Termination for Root Ports
– Full packet transforms (ESP & AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Packet transforms
– One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4
Preliminary Data Sheet
Revision 1.21 - July 9, 2008
AMCC Proprietary