ppc405cr Applied Micro Circuits Corporation (AMCC), ppc405cr Datasheet
ppc405cr
Available stocks
Related parts for ppc405cr
ppc405cr Summary of contents
Page 1
... Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported Description The PowerPC 405CR (PPC405CR 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. ...
Page 2
... PPC405CR – PowerPC 405CR Embedded Processor Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External Peripheral Bus Controller (EBC DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Universal Interrupt Controller (UIC JTAG ...
Page 3
... PPC405CR – PowerPC 405CR Embedded Processor List of Figures Figure 1. PPC405CR Embedded Controller Functional Block Diagram .................................................................. 5 Figure 2. 27mm, 316-Ball E-PBGA Package ......................................................................................................... 10 Figure 3. Package Thermal Specifications ............................................................................................................ 28 Figure 4. 5V-Tolerant I/O Input Current ................................................................................................................. 30 Figure 5. Timing Waveform .................................................................................................................................... 32 Figure 6. Input Setup and Hold Waveform ............................................................................................................. 35 Figure 7. Output Delay and Float Timing Waveform .............................................................................................. 35 List of Tables Table 1 ...
Page 4
... Each part number contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revi- sion level of the part. Refer to the PPC405CR Embedded Processor User’s Manual for details on the register content. Part Number Key ...
Page 5
... Decompression (CodePack™) SDRAM Controller 13-bit addr 32-bit data The PPC405CR is designed using the IBM Microelectronics Blue Logic blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect AMCC Power Mgmt DCRs ...
Page 6
... The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Regis- ters (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr and mfdcr instructions. ...
Page 7
... PPC405CR – PowerPC 405CR Embedded Processor SDRAM Memory Controller The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of sys- tem memory configurations are supported. The memory controller supports up to four logical banks 256MB per bank are supported maximum of 1 GB. Memory timings, address and bank sizes, and memory addressing modes are programmable ...
Page 8
... PPC405CR – PowerPC 405CR Embedded Processor - Buffered memory to peripheral transfers • Four channels • Scatter/Gather capability for programming multiple DMA operations • 8-, 16-, 32-bit peripheral support (OPB and external) • 32-bit addressing • Address increment or decrement • Internal 32-byte data buffering capability • ...
Page 9
... PPC405CR – PowerPC 405CR Embedded Processor Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: • Supports 7 external and 10 internal interrupts • ...
Page 10
... PPC405CR – PowerPC 405CR Embedded Processor Figure 2. 27mm, 316-Ball E-PBGA Package Reserved Area for Ejector Pin Mark x 4 TYP Top View Corner Shape is Chamferred or Rounded Gold Gate Release Corresponds to A1 Ball Location 15.0 TYP 7.5 TYP Notes: 1. All dimensions are in mm. 2. Package available in leaded and lead-free configurations. ...
Page 11
... PPC405CR – PowerPC 405CR Embedded Processor Pin Lists In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. The page number listed gives the page in “ ...
Page 12
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball A10 A15 A20 B19 C18 D17 E10 E11 E16 F20 GND K10 K11 K12 K16 K20 L10 L11 L12 L16 M10 M11 M12 R20 T10 T11 T16 U17 ...
Page 13
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball GPIO1[TS1E] B18 GPIO2[TS2E] D16 GPIO3[TS1O] C17 GPIO4[TS2O] P18 GPIO5[TS3] T17 GPIO6[TS4] W18 GPIO7[TS5] Y19 GPIO8[TS6] W13 GPIO9[TrcClk] Halt E19 HoldAck HoldPri HoldReq IICSCL U15 IICSDA W17 IRQ0[GPIO17] D18 ...
Page 14
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball MemData0 MemData1 K19 MemData2 L20 MemData3 M20 MemData4 M19 MemData5 L18 MemData6 L17 MemData7 N20 MemData8 N19 MemData9 M18 MemData10 M17 MemData11 P20 MemData12 P19 MemData13 N18 MemData14 ...
Page 15
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 D10 PerAddr14 PerAddr15 PerAddr16 B11 PerAddr17 A11 PerAddr18 B12 PerAddr19 D11 PerAddr20 A13 PerAddr21 ...
Page 16
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 ...
Page 17
... PPC405CR – PowerPC 405CR Embedded Processor Table 3. Signals Listed Alphabetically Signal Name Ball SysClk H17 SysErr A18 SysReset D19 TCK TDI TDO TestEn F19 TmrClk B20 TMS TRST H19 UART0_CTS W10 UART0_DCD R18 UART0_DSR U16 UART0_DTR U13 UART0_RI V15 UART0_RTS V20 ...
Page 18
... PPC405CR – PowerPC 405CR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball A1 GND B10 A2 TDI B11 A3 PerAddr0 B12 A4 PerAddr1 B13 A5 PerCS3[GPIO12] B14 A6 Gnd B15 A7 PerAddr9 B16 A8 DMAReq3 B17 A9 PerAddr15 B18 A10 GND B19 A11 PerAddr17 B20 ...
Page 19
... PPC405CR – PowerPC 405CR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball G17 IRQ4[GPIO21] K2 G18 MemClkOut1 K3 G19 Reserved K4 G20 ClkEn1 K5 H1 PerData25 K9 H2 PerData26 K10 H3 PerData31 K11 H4 PerPar3 K12 V H5 K16 DD V H16 K17 DD H17 SysClk ...
Page 20
... PPC405CR – PowerPC 405CR Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball T17 GPIO5[TS3] U18 T18 MemData15 U19 T19 UART0_RX U20 T20 Reserved V1 U1 PerData2 V2 U2 PerData0 V3 U3 MemAddr10 V4 U4 GND V5 U5 ExtAck V6 U6 MemAddr5 V7 U7 ...
Page 21
... PPC405CR to broadcast an address to external slave devices when the PPC405CR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405CR ...
Page 22
... The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed Alphabet- ically” on page 11 for the pin number to which each signal is assigned. ...
Page 23
... MemClkOut0:1 SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer. External Slave Peripheral Interface Peripheral data bus used by PPC405CR when not in external master mode, otherwise used by external master. PerData0:31 Note: PerData0 is the most significant bit (msb) on this bus. ...
Page 24
... DCR register bit. Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved. When the PPC405CR is the bus master, it enables the selected device to drive the bus. Used by the PPC405CR when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved ...
Page 25
... ExtReq is used by an external master to indicate it is prepared to ExtReq transfer data. ExtAck ExtAck is used by the PPC405CR to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external HoldPri master tenure. Used when the PPC405CR needs to regain control of the peripheral BusReq interface from an external master ...
Page 26
... JTAG test clock. The frequency of this input can range from DC to TCK 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG TRST controller and for normal operation of the PPC405CR. System Interface SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset ...
Page 27
... PPC405CR – PowerPC 405CR Embedded Processor Table 6. Signal Functional Description (Sheet Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values. ...
Page 28
... Case temperature under bias Note: All specified voltages are with respect to GND. Figure 3. Package Thermal Specifications The PPC405CR is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E- PBGA package in a convection environment are as follows: Thermal Resistance ...
Page 29
... PPC405CR – PowerPC 405CR Embedded Processor Table 8. Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (2.5V CMOS receivers) Input Logic High (3 ...
Page 30
... PPC405CR – PowerPC 405CR Embedded Processor Figure 4. 5V-Tolerant I/O Input Current 100 0 -100 -200 -300 -400 -500 -600 -700 0.0 1.0 Table 9. Input Capacitance Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O RX only pins 30 2.0 3.0 4.0 Input Voltage (V) Symbol C IN1 C IN2 C IN4 Revision 1.02 – January 11, 2005 Data Sheet 5.0 Maximum Unit Notes 5 ...
Page 31
... PPC405CR – PowerPC 405CR Embedded Processor Table 10. DC Electrical Characteristics Parameter Active Operating Current (V )—133MHz DD Active Operating Current (OV )—133MHz DD Active Operating Current (V )—200MHz DD Active Operating Current (OV )—200MHz DD Active Operating Current (V )—266MHz DD Active Operating Current (OV )—266MHz DD PLL V Input current DD Note: 1. Maximum power is characterized at V running an application designed to maximize power consumption ...
Page 32
... PPC405CR – PowerPC 405CR Embedded Processor Table 11. Clocking Specifications Symbol CPU PF Processor clock frequency C PT Processor clock period C SysClk Input SCF Clock input frequency C SCT Clock period C SCT Clock edge stability (phase jitter, cycle to cycle) CS SCT Clock input high time CH SCT ...
Page 33
... If an external serial clock is used the baud rate is unaf- fected by the modulation. 2. IIC operation is unaffected. Caution the system designer to ensure that any SSCG used with the PPC405CR meets the above requirements and does not adversely affect other aspects of the system. AMCC Revision 1.02 – ...
Page 34
... PPC405CR – PowerPC 405CR Embedded Processor Table 12. Peripheral Interface Clock Timings Parameter PerClk output frequency—133MHz PerClk period—133MHz PerClk output frequency—200MHz PerClk period—200MHz PerClk output frequency—266MHz PerClk period—266MHz PerClk output high time PerClk output low time ...
Page 35
... PPC405CR – PowerPC 405CR Embedded Processor Figure 6. Input Setup and Hold Waveform Clock Inputs Figure 7. Output Delay and Float Timing Waveform Clock max min Outputs OH High (Drive) Float (High-Z) Low (Drive) AMCC T min T min IS IH Valid max min OH Valid Revision 1.02 – ...
Page 36
... PPC405CR – PowerPC 405CR Embedded Processor Notes all of the following I/O Specifications tables a timing value of na means “not applicable” and dc means “don’t care.” 2. See “Test Conditions” on page 31 for output capacitive loading specified at 2.4V; I specified at 0.4V Table 13. I/O Specifications—All speeds ...
Page 37
... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
Page 38
... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
Page 39
... When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ ...
Page 40
... PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR, visit the technical documents area of the AMCC PowerPC web site. ...
Page 41
... PPC405CR – PowerPC 405CR Embedded Processor Document Revision History Revision Date 1.01 08/05/04 1.02 01/11/05 AMCC Initial release Add lead-free part numbers. Revision 1.02 – January 11, 2005 Data Sheet Description 41 ...
Page 42
... PPC405CR – PowerPC 405CR Embedded Processor Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’ ...