ppc405cr Applied Micro Circuits Corporation (AMCC), ppc405cr Datasheet - Page 39

• Manufacturer Part Number: ppc405cr
• Description: Powerpc 405cr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PPC405CR – PowerPC 405CR Embedded Processor
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to
+5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following table lists the strapping pins along with their func-
tions and strapping options. The signal names assigned to the pins for normal operation follow the pin number.
Table 16. Strapping Pin Assignments (Sheet 1 of 2)
AMCC
PLL Tuning
for 6
for 7 < M
for 12 < M
See Note.
PLL Forward Divider
PLL Feedback Divider
PLB Divider from CPU
OPB Divider from PLB
≤
M
≤
≤
≤
1
12 use choice 5
32 use choice 6
7 use choice 3
Function
2
2
2, 3
2
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 010010
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 010100
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 010111
Choice 8; TUNE[5:0] = 100100
Bypass mode
Divide by 3
Divide by 4
Divide by 6
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Option
GPIO1[TS1E]
UART0_Tx
DMAAck0
DMAAck2
HoldAck
W15
C16
B16
B18
Revision 1.02 – January 11, 2005
T4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Ball Strapping
GPIO2[TS2E]
UART0_DTR
DMAAck1
DMAAck3
ExtAck
U13
B17
A14
D16
U5
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Sheet
UART0_RTS
V20
0
1
0
1
0
1
0
1
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