adsst-em-3035k Analog Devices, Inc., adsst-em-3035k Datasheet
adsst-em-3035k
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adsst-em-3035k Summary of contents
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... Sampling Frequency Tamper-Proof Metering Single 5 V Supply GENERAL DESCRIPTION The ADSST-EM-3035 Chipset consists of a fast and accurate 6 channel, 16-bit sigma-delta analog-to-digital converter ADSST-73360AR (ADC), an efficient digital signal processor ADSST-2185KST-133 (DSP), and Metering Software. The ADC and DSP are interfaced together to simultaneously acquire ...
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... ALU operations, I/O memory trans- fers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSST-2185KST-133 operates with instruction cycle time. Every instruction can execute in a single processor cycle. ...
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... The ADSST-2185KST-133 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSST-2185KST-133 SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual, Third Edition. SPORTs are bidirectional and have a separate, double-buffered • ...
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... I Mode Select Input-Checked only During RESET Pin Descriptions The ADSST-2185KST-133 is available in a 100-lead TQFP package. To maintain maximum functionality and reduce pack- age size and pin count, some serial ports, programmable flags, interrupt and external bus pins have dual, multiplexed function- ality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution ...
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... VDD 15 CLKOUT 16 GND 17 VDD BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 REV. 0 100-Lead TQFP Package Pinout ADSST-2185KST-133 TOP VIEW (Not to Scale) –5– ADSST-EM-3035 75 D15 74 D14 73 D13 72 D12 GND 71 70 D11 D10 VDD 66 GND D7/IWR 63 D6/IRD 62 D5/IAL ...
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... This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. Reset The RESET signal initiates a master reset of the ADSST- 2185KST-133. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET dur- ing initial power-up must be held long enough to allow the internal clock to stabilize ...
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... Three-statable pins: A0–A13, D0, D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0, PF7 BR, CLKIN inactive. 9 Idle refers to ADSST-2185KST-133 state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...
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... The ADSST-73360AR is particularly suitable for industrial power metering as each channel samples synchronously, ensur- ing that there is no (phase) delay between the conversions. The ADSST-73360AR also features low group delay conversions on all channels. An on-chip reference voltage is included with a nominal value of 1.2 V. ...
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... Output Sample Rate µs 190 µs 8 kHz Output Sample Rate 6 25 kΩ DMCLK = 16.384 MHz 0 dB –0.1 dB –0.25 dB –0.6 dB –1.4 dB –2.8 dB –4.5 dB –7.0 dB –9.5 dB < –12.5 dB –9– ADSST-EM-3035 = 8 kHz unless otherwise noted A MIN MAX = 8 kHz kHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSST-EM-3035 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... SCLK Output Serial Clock whose rate determines the serial trans- fer rate to/from the ADSST73360AR used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number This integer number being the product of the external master clock rate divider and the serial clock rate divider ...
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... However, because the resolution of the ADSST- 73360LAR ADC is high, and the noise levels from the ADSST-73360AR are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the ADSST-73360AR should be designed so the analog and digital sections are sepa- rated and confined to certain sections of the board ...
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... The microcontroller can use this to verify that the complete metering code has been loaded on the DSP processor properly. The DSP is now ready to provide the computed data on the SPI port. BYTE OF DATA MINIMUM 6 DSP T1 CLOCK CYCLES –13– ADSST-EM-3035 ...
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... Figure 10. Power Up Initialization To reduce the component count, cost and to give designer a greater flexibility in designing, ADSST-EM-3035 has not been provided with any Nonvolatile Memory to store the calibration constants and initialization data. On power up, after the boot loading of the DSP software, the microcontroller provides the DSP with all the initialization data ...
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... Phase Compensation Coefficients Three sets of filter coefficients have been provided which will be automatically selected by the DSP during execution based on the maximum current (Imax). In the ADSST-EM-3035, the Imax is fixed at 20 Amps. Therefore the current ranges have been grouped as: • ...
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... ADSST-EM-3035 DATA from DSP on SPI BUS B Phase Channel_Present R Phase Current Division FlagUnits_flag_R Y Phase Current Division FlagUnits_flag_Y B Phase Current Division FlagUnits_flag_B R Phase Negative Power Flag Y Phase Negative Power Flag B Phase Negative Power Flag R Phase (INDUC/CAP POWER Flag) Y Phase (INDUC/CAP POWER Flag) ...
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... This limit defines the resistance network on the potential REF circuits and the burden resistance on the secondary side of the CT. ADSST-73360AR being a unipolar ADC the ac, poten- tial, and current have to be offset by a desired dc level. The reference design has a dc offset of 2.5 V. This limits the p-p signal range of potential and current to ± ...
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... The error can be calculated by the given formula. General Note About Calibration • It should be noted that ADSST-EM-3035 does not have any permanent memory and hence all the calibration data are to be stored by the microcontroller and provided to the DSP at the time of power up. ...
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... V 0.5 Lagging N Table XIV. Voltage Variation Error PF Min 1.0 MAX 0.5 Lagging MAX Table XV. Frequency Variation Errors PF Min 1.0 MAX 0.5 Lagging MAX –19– ADSST-EM-3035 Metal CT (0.5 Class) Nominal Value V = 230 V ± 300 MAX MAX Hz/60 Hz ± 10 < ± 2°C ...
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... Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Input Voltage . . . . . . . . . . . . . . . . . . . . –0 Output Voltage Swing . . . . . . . . . . . . . –0 Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Model ADSST-EM-3035K 0 to +70ºC 100-Lead Thin Plastic Quad Flat Package [TQFP] (SU-100) Dimensions shown in millimeters 1.20 16.00 SQ ...