adsst-em-3035k Analog Devices, Inc., adsst-em-3035k Datasheet - Page 6

• Manufacturer Part Number: adsst-em-3035k
• Description: Salem Three-phase Electronic Energy Meter
• Manufacturer: Analog Devices, Inc.

ADSST-EM-3035
System Interface
Figure 2 shows typical basic system configurations with the
ADSST-2185KST-133, two serial devices, a byte-wide EPROM
and optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the proces-
sor to connect easily to slow peripheral devices. The ADSST-
2185KST-133 also provides four external interrupts and two serial
ports, or six external interrupts and one serial port. Host Memory
Mode allows access to the full external data bus, but limits address-
ing to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
Recommended Operating Conditions
Parameters
V
T
Operating Temperature
DD
AMB
CONTROLLER
INTERFACE
Supply Voltage
1/2x CLOCK
1/2x CLOCK
SYSTEM
CRYSTAL
CRYSTAL
Ambient
OR
SERIAL
DEVICE
SERIAL
DEVICE
DEVICE
DEVICE
SERIAL
SERIAL
OR
OR
16
Figure 2. Basic System Interface
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
HOST MEMORY MODE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
FULL MEMORY MODE
CLKIN
CLKIN
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/ PF5
IRQL1/ PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/ PF5
IRQL1/ PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
IDMA PORT
SPORT1
SPORT0
SPORT0
SPORT1
ADSST-2185
ADSST-2185
KST-133
KST-133
ADDR13–0
DATA23–0
DATA23–8
PWDACK
PWDACK
Min Max
4.5
0
ADDR0
A Grade
IOMS
IOMS
BMS
PMS
DMS
CMS
BGH
PWD
BMS
PMS
DMS
CMS
BGH
PWD
BR
BG
BR
BG
14
1
5.5
+70
16
24
A
D
13–0
23–16
A
A
D
D
D
10–0
13–0
15–8
23–0
23–8
Min
4.5
–40
B Grade
A0–A21
DATA
DATA
DATA
CS
ADDR
CS
ADDR
(PERIPHERALS)
PM SEGMENTS
DM SEGMENTS
2048 LOCATIONS
Max
5.5
+85
OVERLAY
MEMORY
I/O SPACE
TWO 8K
TWO 8K
MEMORY
BYTE
Unit
V
°C
–6–
Clock Signals
Either a crystal or a TTL-compatible clock signal can clock the
ADSST-2185KST-133.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal
operation. The only exception is while the processor is in the
power-down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to the
processor's CLKIN input. When an external clock is used, the
XTAL input must be left unconnected.
The ADSST-2185KST-133 uses an input clock with a frequency
equal to half the instruction rate; a 20.00 MHz input clock
yields a 25 ns processor cycle (which is equivalent to 40 MHz).
Normally, instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
Because the ADSST-2185KST-133 includes an on-chip oscillator
circuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
Reset
The RESET signal initiates a master reset of the ADSST-
2185KST-133. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET dur-
ing initial power-up must be held long enough to allow the
internal clock to stabilize. If RESET is activated any time after
power-up, the clock continues to run and does not require stabi-
lization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this power-
up sequence, the RESET signal should be held low. On any
subsequent resets, the RESET signal must meet the minimum
pulsewidth specification, t
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended. The master reset sets
all internal stack pointers to the empty stack condition, masks
all interrupts and clears the MSTAT register. When RESET is
released, if there is no pending bus request and the chip is con-
figured for booting, the boot-loading sequence is performed.
The first instruction is fetched from on-chip program memory
location 0x0000 once boot loading completes.
Figure 3. External Crystal Connections
DSP
CLKIN
RSP
.
XTAL
CLKOUT
REV. 0