k9f4g08u0m-y Samsung Semiconductor, Inc., k9f4g08u0m-y Datasheet - Page 32

• Manufacturer Part Number: k9f4g08u0m-y
• Description: 512m X 8 Bits / 1g X 8 Bits Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9K8G08U1M
K9F4G08U0M
Figure 8. Program & Read Status Operation
Figure 7. Random Data Output In a Page
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare
array(1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
R/B
RE
I/Ox
R/B
I/Ox
00h
Col. Add.1,2 & Row Add.1,2,3
80h
5Cycles
Address
Col. Add.1,2 & Row Add.1,2,3
Address & Data Input
Data
30h
t
R
Data Field
10h
Data Output
Spare Field
32
t
PROG
05h
Col. Add.1,2
Address
2Cycles
70h
FLASH MEMORY
E0h
Data Field
I/O
Fail
Data Output
0
Advance
"1"
"0"
Spare Field
Pass