k4m51323pc Samsung Semiconductor, Inc., k4m51323pc Datasheet - Page 7

• Manufacturer Part Number: k4m51323pc
• Description: 4m X 32bit X 4 Banks Mobile Sdram In 90fbga
• Manufacturer: Samsung Semiconductor, Inc.

OPERATING AC PARAMETER
K4M51323PC-S(D)E/G/C/F
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
2. Minimum delay is required to complete write.
3. Maximum burst refresh cycle : 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Auto refresh cycle time
Exit self refresh to active command
Col. address to col. address delay
Number of valid output data
Number of valid output data
Number of valid output data
higher integer.
Parameter
CAS latency=3
CAS latency=2
CAS latency=1
t
t
t
t
t
t
t
t
t
t
t
ARFC
SRFX
RAS
Symbol
RRD
RCD
t
t
CCD
RAS
RDL
DAL
CDL
BDL
RP
RC
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
22.5
22.5
72.5
-75
15
50
-
tRDL + tRP
Version
100
120
-90
18
24
24
50
74
15
80
1
1
1
2
1
-1L
18
27
27
50
77
0
Mobile-SDRAM
Unit
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ns
ns
ns
ea
-
February 2006
Note
1
1
1
1
1
2
2
2
3
4
5