r8a66162sp Renesas Electronics Corporation., r8a66162sp Datasheet - Page 2

• Manufacturer Part Number: r8a66162sp
• Description: 32-bit Led Driver With Shift Register And Latch
• Manufacturer: Renesas Electronics Corporation.

R8A66162SP
PIN CONFIGURATION ( TOP VIEW )
FUNCTIONAL DESCRIPTION
The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and
maintains high noise margin as well as high output current and high speed required to drive LEDs.
Each shift register bit consists of a flip-flop for shifting and an output latch.
The shift operation takes place when the shift clock input CK changes from low-level to high-level.
The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is
shifted in sequence when a pulse is applied to CK.
If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched.
The parallel data outputs Q
To expand the number of bits, use the serial data output SQ
the 32nd bit.
If the direct set input S
If the high-level input is applied to the output enable input OE, Q
but SQ
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 2 of 7
32
is not set to the high-impedance state. The shift operation is not affected when OE is changed.
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS
SERIAL DATA INPUT
SERIAL DATA INPUT
OUTPUT ENABLE INPUT
OUTPUT ENABLE INPUT
LATCH ENABLE INPUT
LATCH ENABLE INPUT
DIRECT SET INPUT
DIRECT SET INPUT
SHIFT CLOCK INPUT
SHIFT CLOCK INPUT
SERIAL DATA OUTPUT
SERIAL DATA OUTPUT
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS
D
is turned low-level, Q
1
~Q
32
are open-drain outputs.
GND
GND
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
GND
GND
V
V
A
A A
OE
OE
OE
OE
LE
LE
LE
LE
SD
SD
SD
SD
CK
CK
CK
V
V
GND
GND
SQ
SQ
SQ
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
GND
GND
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
CC
CC
CC
CC
27
27
27
27
28
28
28
28
29
29
29
29
30
30
30
30
31
31
31
31
32
32
32
32
32
32
32
1
1
1
1 1
2
2
2
2 2
3
3
3
3 3
4
4
4
4 4
5
5
5
5 5
6
6
6
6 6
7
7
7
7 7
8
8
8
8 8
9
9
9
9 9
10
10
10
10
10
11
11
11
11
11
12
12
12
12
12
13
13
13
13
13
14
14
14
14
14
15
15
15
15
15
16
16
16
16
16
17
17
17
17
17
18
18
18
18
18
19
19
19
19
19
20
20
20
20
20
21
21
21
21
21
22
22
22
22
22
23
23
23
23
23
24
24
24
24
24
1
~Q
32
and SQ
32
32
are set. Then shift register and latches are set.
which shows the output of the shift register of
48
48
48
48
48
47
47
47
47
47
46
46
46
46
46
45
45
45
45
45
44
44
44
44
44
43
43
43
43
43
42
42
42
42
42
41
41
41
41
41
40
40
40
40
40
39
39
39
39
39
38
38
38
38
38
37
37
37
37
37
36
36
36
36
36
35
35
35
35
35
34
34
34
34
34
33
33
33
33
33
32
32
32
32
32
31
31
31
31
31
30
30
30
30
30
29
29
29
29
29
28
28
28
28
28
27
27
27
27
27
26
26
26
26
26
25
25
25
25
25
1
~Q
32
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
GND
GND
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
V
V
GND
GND
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
GND
GND
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
CC
CC
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
25
25
25
25
26
26
26
26
are set to the high-impedance state,
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS
PARALLEL
PARALLEL
DATA
DATA
OUTPUTS
OUTPUTS