mt58l512v18p ETC-unknow, mt58l512v18p Datasheet - Page 19

• Manufacturer Part Number: mt58l512v18p
• Description: 512k 256k 32/36 Pipelined, Syncburst Sram
• Manufacturer: ETC-unknow

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1)(0°C
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (V
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
2. Measured as HIGH above V
3. This parameter is measured with output load as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
Figure 3 for 2.5V I/O (V
discussion on these parameters.
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required
setup and hold times.
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
T
A
+70°C; V
DD
DD
= +3.3V +0.3V/-0.165V)
Q = +2.5V +0.4V/-0.125V) unless otherwise noted.
IH
and LOW below V
SYMBOL
t
t
t
t
t
t
t
t
KQHZ
t
ADSH
OEHZ
t
t
KQLZ
OELZ
ADSS
t
t
KQX
OEQ
t
t
AAH
t
t
t
t
t
AAS
t
CEH
f
t
WH
CES
KQ
WS
AH
DH
KC
KH
KF
KL
AS
DS
MIN
IL
6.0
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
0
.
19
6
PIPELINED, SCD SYNCBURST SRAM
MAX
166
3.5
3.5
3.5
3.5
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
7.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
.5
0
0
-7.5
MAX
133
4.2
4.2
4.0
4.2
MIN
DD
3.0
3.0
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
10
0
Q = +3.3V +0.3V/-0.165V) and
-10
MAX
100
5.0
5.0
5.0
4.5
©2002, Micron Technology, Inc.
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
NOTES
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
2
2
3
7