gvt7164d18 ETC-unknow, gvt7164d18 Datasheet

gvt7164d18

Manufacturer Part Number

gvt7164d18

Description

Synchronous Burst Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT7164D18.pdf (13 pages)

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FEATURES

• Fast access times: 5, 6, 7, and 8ns

• Fast clock speed: 100, 83, 66, and 50 MHz

• Provide high performance 3-1-1-1 access rate

• Fast OE# access times: 5, and 6ns

• Optimal for depth expansion (one cycle chip deselect to

• Single +3.3V -5 to +10% power supply

• 5V tolerant inputs except I/O’s

• Clamp diodes to VSSQ at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Three chip enables for depth expansion and address

• Address, control, input, and output pipeline registers

• Internally self-timed WRITE CYCLE

• WRITE pass-through capability

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• High density, high speed packages

• Low capacitive bus loading

• High 30pF output drive capability at rated access time

OPTIONS

• Timing

• Packages

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 2/98

GALVANTECH

BURST SRAM

PIPELINED OUTPUT

SYNCHRONOUS

eliminate bus contention)

pipeline

5ns access/10ns cycle

6ns access/12ns cycle

7ns access/15ns cycle

8ns access/20ns cycle

100-pin PQFP

Fax (408) 566-0699

MARKING

-5

-6

-7

-8

, INC.

64K X 18 SYNCHRONOUS BURST SRAM

GENERAL DESCRIPTION

employs high-speed, low power CMOS designs using

advanced double-layer polysilicon, double-layer metal

technology. Each memory cell consists of four transistors and

two high valued resistors.

cells with advanced synchronous peripheral circuitry and a 2-

bit counter for internal burst operation. All synchronous

inputs are gated by registers controlled by a positive-edge-

triggered clock input (CLK). The synchronous inputs include

all addresses, all data inputs, address-pipelining chip enable

(CE#), depth-expansion chip enables (CE2# and CE2), burst

control inputs (ADSC#, ADSP#, and ADV#), write enables

(WEL#, WEH#, and BWE#), and global write (GW#).

and burst mode control (MODE). The data outputs (Q),

enabled by OE#, are also asynchronous.

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one to four bytes wide as controlled by the write control

inputs. Individual byte write allows individual byte to be

written. WEL# controls DQ1-DQ8 and DQP1. WEH#

controls DQ9-DQ16 and DQP2. WEL#, and WEH# can be

active only with BWE# being LOW. GW# being LOW causes

all bytes to be written. This device also incorporates WRITE

pass-through capability and pipelined enable circuit for better

system performance.

All inputs and outputs are TTL-compatible. The device is

ideally suited for 486, Pentium

systems and for systems that are benefited from a wide

synchronous data bus.

The Galvantech Synchronous Burst SRAM family

The GVT7164D18 SRAM integrates 65536x18 SRAM

Asynchronous inputs include the output enable (OE#)

Addresses and chip enables are registered with either

Address, data inputs, and write controls are registered on-

The GVT7164D18 operates from a +3.3V power supply.

64K x 18 SRAM

+3.3V SUPPLY,FULLY REGISTERED

INPUTS AND OUTPUTS, BURST COUNTER

, 680x0, and PowerPC

GVT7164D18

PowerPC is a trademark of IBM Corporation.

Pentium is a trademark of Intel Corporation.

Galvantech, Inc. reserves the right to change

products or specifications without notice.

Related parts for gvt7164d18

gvt7164d18 Summary of contents

Page 1

... This device also incorporates WRITE pass-through capability and pipelined enable circuit for better system performance. The GVT7164D18 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium systems and for systems that are benefited from a wide synchronous data bus ...

Page 2

... X 18 SYNCHRONOUS BURST SRAM UPPER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE Input Register Address Register CLR Binary Counter & Logic 2 GVT7164D18 Q OUTPUT REGISTER DQ1- DQ16 DQP1, DQP2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 3

... All synchronous inputs must meet setup and hold times around the clock’s rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP#. Chip Enable: This active LOW input is used to enable the device. 3 GVT7164D18 A10 ...

Page 4

... A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A...A10 BWE# WEL# WEH GVT7164D18 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 5

... PRESENT CYCLE OPERATION CE# 2,3 Initiate READ cycle L Register A(n D(n-1) 2,3 No new cycle D(n-1) 2,3 No new cycle HIGH new cycle D(n-1) for one byte 5 GVT7164D18 ADV# WRITE# OE# CLK L-H High L-H High L-H High L-H High L-H ...

Page 6

... SB3 I 30 SB4 ; VCC = MAX; IH CONDITIONS SYMBOL MHz C I VCC = 3. CONDITIONS SYMBOL PLCC TYP TQFP TYP Still air, soldered on 4. 1.125 inch 4-layer PCB JC 6 GVT7164D18 MIN MAX UNITS 2.0 VCCQ+0.3 V -0.3 0 2.4 V 0.4 V 3.1 3 ...

Page 7

... KQX KQLZ 3 3 KQHZ OEQ OELZ 0 0 OEHZ 2.5 2.5 2 0.5 0.5 0.5 TYP MAX KQ 0.016 7 GVT7164D18 -8 -7 MAN MIN MAN UNITS NOTES ...

Page 8

... See Figures 1 and 2 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig / increases with greater t KQHZ is less o C and 20ns cycle time. 8 GVT7164D18 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 351 Fig. 2 OUTPUT LOAD EQUIVALENT Galvantech, Inc ...

Page 9

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 8, 1998 Rev. 2/98 , INC. 64K X 18 SYNCHRONOUS BURST SRAM READ TIMING OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ 9 GVT7164D18 t H Q(A2+2) Q(A2+3) Q(A2) BURST READ Galvantech, Inc. reserves the right to change products or specifications without notice. Q(A2+1) ...

Page 10

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 8, 1998 Rev. 2/98 , INC. 64K X 18 SYNCHRONOUS BURST SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 10 GVT7164D18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Galvantech, Inc. reserves the right to change products or specifications without notice. D(A3+2) ...

Page 11

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 8, 1998 Rev. 2/98 , INC. 64K X 18 SYNCHRONOUS BURST SRAM READ/WRITE TIMING Q(A1) Q(A2) D(A3) Q(A3) Pass Through Single Write 11 GVT7164D18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 12

... GALVANTECH 100 Pin PQFP Package Dimensions # 1 2.80 + 0.25 Note: All dimensions in Millimeters February 8, 1998 Rev. 2/98 , INC. 64K X 18 SYNCHRONOUS BURST SRAM 17.20 + 0.30 14.00 + 0.10 0.65 Basic 12 GVT7164D18 0.30 + 0.10 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 13

... Galvantech Prefix Part Number February 8, 1998 Rev. 2/98 , INC. 64K X 18 SYNCHRONOUS BURST SRAM 13 GVT7164D18 Speed (5 = 5ns access/10ns cycle 6 = 6ns access/12ns cycle 7 = 7ns access/15ns cycle, 8= 8ns access/20ns cycle) Package (Q = 100 PIN PQFP) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

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