gvt7164d18 ETC-unknow, gvt7164d18 Datasheet - Page 4

• Manufacturer Part Number: gvt7164d18
• Description: Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (continued)
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE =GND)
PARTIAL TRUTH TABLE FOR READ/WRITE
February 8, 1998
Rev. 2/98
GALVANTECH
1-3, 6, 7, 16, 25, 28-
30, 38, 39, 42, 43,
49-53,56, 57, 66, 75,
78-79, 95, 96
READ
READ
WRITE one byte
5, 10, 21, 26, 55, 60,
4, 11, 20, 27, 54, 61,
69, 72, 73, 8, 9, 12,
FUNCTION
58, 59, 62, 63, 68,
13, 18, 19, 22, 23
14, 15, 41,65, 91
17, 40, 67, 90
First Address
First Address
QFP PINS
(external)
(external)
74, 24
70, 77
71, 76
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A11
85
86
93
94
95
31
64
DQ1-DQ16
SYMBOL
ADSP#
ADSC#
MODE
DQP1,
VCCQ
VSSQ
DQP2
ADV#
VCC
Second Address
Second Address
CE2
OE#
VSS
NC
ZZ
(internal)
(internal)
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
GW#
Synchronous
Synchronous
Synchronous
Synchronous
Input-Static Snooze: LOW or NC for normal operation. High for low power standby.
I/O Ground Output Buffer Ground: GND
H
H
H
I/O Supply Output Buffer Supply: +3.3V -5 to +10%
Ground
Output
Output
Supply
TYPE
input-
Input-
Input-
Input-
Input-
Static
Input/
Input/
Input
-
, INC.
BWE#
H
Chip enable: This active HIGH input is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data
output drivers.
Address Advance: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address
advance).
Address Status Processor: This active LOW input, along with CE# being
LOW, causes a new external address to be registered and a READ cycle
is initiated using the new address.
Address Status Controller: This active LOW input causes device to be de-
selected or selected along with new external address to be registered. A
READ or WRITE cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects
linear burst. A NC or HIGH on this pin selects interleaved burst.
Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-DQ16.
Input data must meet setup and hold times around the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity
bit for DQ9-DQ16.
Power Supply: +3.3V -5 to +10%
Ground: GND
No Connect: These signals are not internally connected.
L
L
Third Address
Third Address
(internal)
(internal)
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
WEL#
X
H
L
64K X 18 SYNCHRONOUS BURST SRAM
WEH#
4
X
H
H
Fourth Address
Fourth Address
DESCRIPTION
(internal)
(internal)
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A11
Galvantech, Inc. reserves the right to change products or specifications without notice.
GVT7164D18