gvt72128a8 ETC-unknow, gvt72128a8 Datasheet - Page 2

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gvt72128a8

Manufacturer Part Number
gvt72128a8
Description
With Single Chip Enable Revolutionary Pinout
Manufacturer
ETC-unknow
Datasheet
TRUTH TABLE
PIN DESCRIPTIONS
December 30, 1996
Rev. 12/96
GALVANTECH
READ
WRITE
OUTPUT DISABLE
STANDBY
4, 3, 2, 1, 32, 31, 30,
29, 21, 20, 19, 18,
17, 16, 15, 14, 13
MODE
22, 23, 26, 27
FUNCTIONAL BLOCK DIAGRAM
Numbers
6, 7,10, 11,
SOJ Pin
A16
8, 24
9, 25
A0
12
28
5
SYMBOL
DQ1-DQ8
A0-A16
WE#
VCC
CE#
OE#
VSS
CE#
L
L
L
H
Input/Output SRAM Data I/O: Data inputs and data outputs
TYPE
Supply
Supply
WE#
Input
Input
Input
Input
H
H
X
L
, INC.
COLUMN DECODER
Addresses Inputs: These inputs determine which cell is addressed.
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW
for a WRITE cycle and HIGH for a READ cycle.
Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the
chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into
standby power mode.
Output Enable: This active LOW input enables the output drivers.
Power Supply: 5V
Ground
OE#
512 ROWS X 256 X 8
X
H
X
L
M E M O R Y A R R A Y
C O L U M N S
HIGH-Z
HIGH-Z
DQ
Q
D
+
2
10%
REVOLUTIONARY PINOUT 128K X 8
STANDBY
POWER
ACTIVE
ACTIVE
ACTIVE
DESCRIPTION
Galvantech, Inc. reserves the right to change products or specifications without notice.
POWER
DOWN
GVT72128A8
VCC
VSS
DQ1
DQ8
CE#
WE#
OE#

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