k6f2016u4e-f Samsung Semiconductor, Inc., k6f2016u4e-f Datasheet
k6f2016u4e-f
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k6f2016u4e-f Summary of contents
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... K6F2016U4E Family Document Title 128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial Draft 1.0 Finalize - Change I from 21 to 26mA for 55ns product. CC2 - Change I from 17 to 20mA for 70ns product. CC2 - Remove "A1 Index Mark" of 48-TBGA package bottom side 2 ...
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... Power Supply Voltage: 2.7~3.3V Low Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-TBGA-6.00x7.00 PRODUCT FAMILY Product Family Operating Temperature K6F2016U4E-F Industrial(-40~ The parameter is measured with 30pF test load. 2. Typical values are measured at V =3.0V, T =25 C and not 100% tested. CC ...
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... K6F2016U4E Family PRODUCT LIST Part Name K6F2016U4E-EF55 K6F2016U4E-EF70 FUNCTIONAL DESCRIPTION means don t care.(Must be low or high state.) ...
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... K6F2016U4E Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note =- otherwise specified Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. ...
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... K6F2016U4E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): C =100pF+1TTL L C =30pF+1TTL L AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product:T Parameter List Read Cycle Time ...
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... K6F2016U4E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6F2016U4E Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in High-Z Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out (WE Controlled CW( WP(1) t AS( WHZ (CS Controlled CW(2) AS( WP( Data Valid ...
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... K6F2016U4E Family TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out High-Z NOTES (WRITE CYCLE wri e occurs during the overlap low CS and low WE. A write begins when CS goes low and WE goes low with asserting for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi- tion when CS goes high and WE goes high ...
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... K6F2016U4E Family PACKAGE DIMENSION 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View B #A1 Side View D C Min Typ A - 0.75 B 5.90 6. 3.75 C 6.90 7. 5.25 D 0.40 0.45 E 0.80 0. 0.58 E2 0.27 0. Bottom View Max - Notes. 6.10 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ ...