74ls194a National Semiconductor Corporation, 74ls194a Datasheet

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74ls194a

Manufacturer Part Number
74ls194a
Description
4-bit Bidirectional Universal Shift Register
Manufacturer
National Semiconductor Corporation
Datasheet

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C 1995 National Semiconductor Corporation
54LS194A DM74LS194A 4-Bit
Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register they feature parallel inputs parallel outputs
right-shift and left-shift serial inputs operating-mode-control
inputs and a direct overriding clear line The register has
four distinct modes of operation namely
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs S0
and S1 high The data is loaded into the associated flip-
flops and appear at the outputs after the positive transition
of the clock input During loading serial data flow is inhibit-
ed
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low
Connection Diagram
Parallel (broadside) load
Shift right (in the direction Q
Shift left (in the direction Q
Inhibit clock (do nothing)
D
TL F 6407
See NS Package Number E20A J16A M16A N16E or W16A
A
toward Q
toward Q
54LS194ALMQB DM74LS194AM or DM74LS194AN
Order Number 54LS194ADMQB 54LS194AFMQB
A
D
)
)
Dual-In-Line Package
Serial data for this mode is entered at the shift-right data
input When S0 is low and S1 is high data shifts left syn-
chronously and new data is entered at the shift-left serial
input
Clocking of the flip-flop is inhibited when both mode control
inputs are low
Features
Y
Y
Y
Y
Parallel inputs and outputs
Four operating modes
Positive edge-triggered clocking
Direct overriding clear
Synchronous parallel load
Right shift
Left shift
Do nothing
TL F 6407 – 1
RRD-B30M105 Printed in U S A
June 1989

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74ls194a Summary of contents

Page 1

... Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low Connection Diagram Order Number 54LS194ADMQB 54LS194AFMQB 54LS194ALMQB DM74LS194AM or DM74LS194AN See NS Package Number E20A J16A M16A N16E or W16A C 1995 National Semiconductor Corporation TL F 6407 Serial data for this mode is entered at the shift-right data ...

Page 2

... Max Max Max 54LS (Note 5) DM74 b V Max (Note DM74LS194A Units Min Nom Max MHz ...

Page 3

Switching Characteristics Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay Time PLH Low to High Level Output t Propagation Delay Time PHL High to Low Level Output t Propagation Delay Time PHL High to Low Output Note 1 ...

Page 4

Timing Diagram Typical Clear Load Right-Shift Left-Shift Inhibit and Clear Sequences 6407 – 3 ...

Page 5

5 ...

Page 6

Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS194ALMQB NS Package Number E20A Order Number 54LS194ADMQB NS Package Number J16A 6 ...

Page 7

... Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS194AM NS Package Number M16A Order Number DM74LS194AN NS Package Number N16E 7 ...

Page 8

Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR ...

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