cxm3540xr Sony Electronics, cxm3540xr Datasheet

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cxm3540xr

Manufacturer Part Number
cxm3540xr
Description
High Linearity Dp4t Antenna Switch For Gsm/umts/cdma
Manufacturer
Sony Electronics
Datasheet

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High Linearity DP4T Antenna Switch for GSM/UMTS/CDMA
Description
Features
Package
Structure
The CXM3540XR is a high power and high linearity DP4T antenna switch for GSM/UMTS/CDMA applications.
The low insertion loss on transmit means increased talk time as the Tx power amplifier can be operated at a
lower output level.
The Integrated logic decoder reduces component count and simplifies PCB layout by allowing direct connection
of the switch to digital base band control lines with the CMOS logic levels.
Sony GaAs JPHEMT MMIC Process is used.
(Applications: GSM/UMTS GSM/CDMA dual mode handsets, CDMA handsets, UMTS handsets)
Small package 22-pin XQFN (2.4mm × 3.3mm × 0.35mm) (Typ.)
GaAs JPHEMT MMIC
This IC is ESD sensitive device. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Low insertion loss: 0.30dB (typ.) @34dBm (Cellular Band)
High linearity: IIP3 = 70dBm
Low voltage operation V
No DC blocking capacitors
Lead-Free and RoHS compliant
0.35dB (typ.) @32dBm (PCS Band)
DD
= 2.5V
- 1 -
CXM3540XR
E08653

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cxm3540xr Summary of contents

Page 1

... High Linearity DP4T Antenna Switch for GSM/UMTS/CDMA Description The CXM3540XR is a high power and high linearity DP4T antenna switch for GSM/UMTS/CDMA applications. The low insertion loss on transmit means increased talk time as the Tx power amplifier can be operated at a lower output level. The Integrated logic decoder reduces component count and simplifies PCB layout by allowing direct connection of the switch to digital base band control lines with the CMOS logic levels ...

Page 2

Absolute Maximum Ratings Bias voltage Control voltage Input power Max. Operating temperature Storage temperature Maximum power dissipation 25mm × 25mm × t: 0.8mm Mounted on standard board (FR- ( Vctl 4 V (Ta ...

Page 3

Block Diagram Pin Configuration GND RF6 GND GND RF5 GND GND RF5 RF6 XQFN-22P PKG (2.4mm × 3.3mm × 0.4mm Max.) 15 Top View 16 17 ...

Page 4

Pin Description Pin No. Symbol 1 CTLD 2 GND 3 GND 4 RF4 5 GND 6 RF3 7 GND 8 RF2 9 GND 10 RF1 11 GND Truth Table State CTLA CTLB CTLC CTLD ...

Page 5

Electrical Characteristics ° ( 2.8V, Vctl = 0/1.8V) DD Item Symbol Insertion loss IL Isolation ISO. VSWR VSWR 2fo 3fo 2fo 3fo Harmonics 2fo 3fo 2fo 3fo P 0.2dB compression P 0.2dB input power IMD3 ...

Page 6

Recommended Circuit Note blocking capacitors are required on all RF ports levels of all RF ports are GND. 3. L1, L2, C1 and C2 are recommended on Ant port for ESD ...

Page 7

Package Outline (Unit: mm) LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS - 7 - SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm Sony Corporation ...

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