ADF4116 Analog Devices, ADF4116 Datasheet
ADF4116
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ADF4116 Summary of contents
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... CE RF PLL Frequency Synthesizers ADF4116/ADF4117/ADF4118 GENERAL DESCRIPTION The ADF4116 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and down- conversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P ...
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... LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL POWER SUPPLIES ( ADF4116 ADF4117 ADF4118 I P Low-Power Sleep Mode ≤ V ≤ 6.0 V; AGND = DGND = CPGND = Version B Chips Unit 80/550 80/550 MHz min/max 0.1/1.2 0.1/1.2 GHz min/max 0.1/3.0 0.1/3.0 GHz min/max 0 ...
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... Guaranteed by design. Sample tested to ensure compliance for ADF4116 = 540 MHz The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer ( MHz @ 0 dBm) ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu- late on the human body and test equipment and can discharge without detection. Although the ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. CSP θ ...
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... V and used to drive a VCO with a tuning range ADF4116/ADF4117/ADF4118 PIN FUNCTION DESCRIPTIONS to the external loop filter, which in turn drives PIN CONFIGURATION TSSOP ADF4116 MUXOUT CPGND 3 14 ADF4117 ADF4118 AGND TOP VIEW 5 DATA (Not to Scale) RF ...
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... ADF4116/ADF4117/ADF4118 –Typical Performance Characteristics FREQ- PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE- UNIT GHz S MA FREQ MagS11 AngS11 FREQ 0.05 0.89207 –2.0571 0.95 0.10 0.8886 –4.4427 1.00 0.15 0.89022 –6.3212 1.05 0.20 0.96323 –2.1393 1.10 0.25 0.90566 –12.13 1.15 0.30 0.90307 –13.52 1.20 0.35 0.89318 –15.746 1.25 0.40 0.89806 –18.056 1.30 0.45 0.89565 –19.693 1 ...
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... R = –40dBc/Hz L –40 –50 2.0 rms –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 1.75GHz CARRIER ADF4116/ADF4117/ADF4118 –10 –20 –30 –40 –50 –60 –70 –90.67dBc –80 –90 –100 +400kHz –60kHz –10 –20 – ...
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... ADF4116/ADF4117/ADF4118 REFERENCE –10 LEVEL = –9.3dBm I = 1mA CP PFD FREQUENCY = 1MHz –20 LOOP BANDWIDTH = 100kHz –30 RES. BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz –40 SWEEP = 1.4 SECONDS –50 AVERAGES = 4 –60 –70 –80 –90 –100 –2MHz –1MHz 2800MHz –130 –135 –140 –145 –150 –155 – ...
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... V – Volts CP RF INPUT STAGE The RF input stage is shown in Figure followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler COUNTER RF ADF4116/ADF4117/ADF4118 50 100 150 PRESCALER OUTPUT FREQUENCY – MHz 4.0 4.5 5.0 1.6V BIAS AV GENERATOR DD 500 500 ...
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... PB + A). The dual-modulus prescaler takes the CML clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is program- mable. It can be set in software to 8/9 for the ADF4116, and set to 32/33 for the ADF4117 and ADF4118 based on a synchronous 4/5 core. ...
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... INPUT SHIFT REGISTER The ADF4116 family digital section includes a 21-bit input shift register, a 14-bit R counter and an 18-bit N counter, comprising a 5-bit A counter and a 13-bit B counter. Data is clocked into the 21-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE ...
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... ADF4116/ADF4117/ADF4118 TEST MODE BITS DB20 DB19 DB18 DB17 DB16 DB15 LDP R14 TEST MODE BITS SHOULD BE SET TO 0000 FOR NORMAL OPERATION LDP OPERATION 0 3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET ...
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... CURRENT SETTINGS 250 1mA ADF4116/ADF4117/ADF4118 Table IV. AB Counter Latch Map DB13 DB12 DB11 DB10 DB9 DB8 DB7 ADF4116 • • • • ADF4117/ADF4118 0 0 • • • • ...
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... ADF4116/ADF4117/ADF4118 RESERVED DB20 DB19 DB18 DB17 DB16 DB15 X PD2 TC4 CE PIN PD2 PD1 MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN TC4 TC3 ...
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... ADF4116/ADF4117/ADF4118 MUXOUT CONTROL DB7 DB6 DB5 DB4 DB3 DB2 DB1 PD1 F1 C2 (1) COUNTER F1 OPERATION 0 NORMAL COUNTERS 1 HELD IN RESET OUTPUT THREE-STATE OUTPUT ...
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... Fastlock is enabled, this bit determines which Fastlock Mode is used. If the Fastlock Mode bit is “0” then Fastlock Mode 1 is selected and if the Fastlock Mode bit is “1,” then Fastlock Mode 2 is selected. If Fastlock is not enabled (DB9 = “0”), then DB11 (ADF4116) determines the state of the FL output same as that programmed to DB11 ...
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... Latching the first N counter data after the initialization word will activate the same internal reset pulse. Successive N loads will not trigger the internal reset pulse unless there is another initialization. ADF4116/ADF4117/ADF4118 The CE Pin Method Apply Bring CE low to put the device into power-down ...
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... SHUTDOWN CIRCUIT The attached circuit in Figure 8 shows how to shut down both the ADF4116 family and the accompanying VCO. The ADG702 switch goes open circuit when a Logic 1 is applied to the IN input. The low-cost switch is available in both SOT-23 and IN micro SOIC packages. ...
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... RF IN 100pF INTERFACING The ADF4116 family has a simple SPI-compatible serial inter- face for writing to the device. SCLK, SDATA and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will get transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table ...
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... The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4116 family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written the LE input should be brought high to complete the transfer ...