IDT70V9289L12PF IDT [Integrated Device Technology], IDT70V9289L12PF Datasheet - Page 2

• Manufacturer Part Number: IDT70V9289L12PF
• Description: HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Description:
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Pin Configuration
NOTES:
1. All V
2. All V
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit
DD
SS
pins must be connected to ground.
pins must be connected to power supply.
CNTEN
CNTEN
ADS
CLK
ADS
CLK
A
A
A
A
A
A
A
A
V
A
A
V
A
A
A
A
A
A
A
A
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
7R
6R
5R
4R
3R
2R
1R
0R
DD
9R
8R
SS
0L
1L
2L
3L
4L
5L
6L
7L
8L
9L
R
R
R
L
L
L
03/28/03
(1,2,3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128-Pin TQFP
70V9389PRF
PK-128-1
Top View
6.42
2
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 500mW of power.
(5)
(4)
With an input data register, the IDT70V9389/289 has been optimized
Industrial & Commercial Temperature Ranges
101
102
100
85
82
78
76
74
99
98
97
96
95
94
93
92
91
90
89
88
87
86
84
83
81
80
79
77
75
73
72
71
70
69
68
67
66
65
4856 drw 02
I/O
I/O
V
NC
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
V
I/O
V
I/O
I/O
I/O
V
V
I/O
I/O
V
I/O
I/O
V
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
NC
I/O
I/O
V
SS
DD
SS
DD
SS
DD
SS
SS
DD
DD
12R
11R
10R
9R
8R
7R
6R
5R
4R
3R
2R
1R
0R
0L
1L
2L
3L
4L
5L
6L
7L
8L
9L
10L
11L
12L
0
and CE
1,
permits the