IDT7133 IDT [Integrated Device Technology], IDT7133 Datasheet
IDT7133
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IDT7133 Summary of contents
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... Industrial temperature range (–40°C to +85°C) is available for selected speeds The IDT7133/7143 are high-speed Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM “MASTER” Dual-Port RAM together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the ...
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... The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP. Military grade product is manufactured in compliance with the ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM 10L R/W L LLB (1) R/W LUB I/O I I/O I I/O I I/O I I/O I I/O 10L Pin 1 Designator A B NOTES: 1 ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to +150 STG Temperature (3) P Power 2.0 T Dissipation I DC Output 50 OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter Dynamic Operating CC , Outputs Disabled IL Current (3) (Both Ports Active MAX CE and CE I Standby Current SB1 L R (Both Ports - TTL (3) Level Inputs MAX CE and CE I Standby Current SB2 = V "A" IL (3) (One Port - TTL ...
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... RC 4. 2746 drw 05 5V 1250 DATA OUT 775 30pF Figure 1. AC Output Test Load 5V 270 BUSY 30pF 2746 drw 06 Figure 3. BUSY Output Load (IDT7133 only) Max. Unit ___ V µA 4000 1500 ___ V ___ V 2746 tbl 08 ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) t Output Low-Z Time LZ (1,2) t Output High-Z Time ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE CE OE DATA OUT CURRENT I SB NOTES: 1. Timing depends on which signal is asserted last CE. ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol Parameter WRITE CYCLE (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM Symbol BUSY TIMING (For MASTER 71V33) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable t BAC BUSY Disable Time from Chip Enable t BDC (1) t Write Pulse to Data Delay ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM ADDRESS ( (9) R DATA OUT DATA IN CE ADDRESS CE ( (9) R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W going HIGH to the end of the write cycle. ...
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... BUSY "B" R/W "B" NOTES: must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master BUSY is asserted on port "B" blocking R/W , until BUSY "B" 3. All timing is the same for left and right ports. Port " ...
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... All timing is the same for left and right ports. Port " is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted APS (IDT7133 only). Military, Industrial and Commercial Temperature Ranges ADDRESSES MATCH t ...
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... BUSY signal as a write inhibit signal. Thus on the IDT7133 RAM the BUSY pin is an output and on the IDT7143 RAM, the BUSY pin is an input (see Figure 3). Military, Industrial and Commercial Temperature Ranges ...
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... L MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs on the IDT7133 (MASTER). Both are L R inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. “H” if the inputs to the opposite port became stable after the is not met, either BUSY address and enable inputs of this port ...
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... IDT7133SA/LA, IDT7143SA/LA High-Speed Dual-Port RAM IDT XXXX XX XX Device Power Speed Package Type 12/18/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 2 corrected PN100 pinout 2/17/99: Corrected PF ordering code 3/9/99: Cosmetic and typographical corrections ...