IC GATE NAND QUAD 2INPUT 14DIP

MC74HC00ANG

Manufacturer Part NumberMC74HC00ANG
DescriptionIC GATE NAND QUAD 2INPUT 14DIP
ManufacturerON Semiconductor
Series74HC
MC74HC00ANG datasheets
 


Specifications of MC74HC00ANG

Logic TypeNAND GateNumber Of Inputs2
Number Of Circuits4Current - Output High, Low5.2mA, 5.2mA
Voltage - Supply2 V ~ 6 VOperating Temperature-55°C ~ 125°C
Mounting TypeThrough HolePackage / Case14-DIP (0.300", 7.62mm)
ProductNANDLogic Family74HC
High Level Output Current- 5.2 mALow Level Output Current5.2 mA
Propagation Delay Time75 nsSupply Voltage (max)6 V
Supply Voltage (min)2 VMaximum Operating Temperature+ 125 C
Mounting StyleThrough HoleMinimum Operating Temperature- 55 C
Circuit TypeLow-Power SchottkyCurrent, Supply40 μA
Function Type2-InputsLogic FunctionNAND Gate
Package TypePDIP-14Temperature, Operating, Range-55 to +125 °C
Voltage, Supply2 to 6 VOutput Current5.2mA
No. Of Inputs2Supply Voltage Range2V To 6V
Logic Case StyleDIPNo. Of Pins14
Operating Temperature Range-55°C To +125°CFilter TerminalsDIP
Rohs CompliantYesFamily TypeHC
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesMC74HC00ANGOS
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MC74HC00A
Quad 2-Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 32 FETs or 8 Equivalent Gates
Pb−Free Packages are Available
LOGIC DIAGRAM
1
A1
2
B1
4
A2
5
B2
9
A3
10
B3
12
A4
13
B4
PIN 14 = V
PIN 7 = GND
Pinout: 14−Lead Packages (Top View)
V
B4
A4
Y4
CC
14
13
12
11
1
2
3
4
A1
B1
Y1
A2
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 11
3
Y1
6
Y2
Y = AB
8
Y3
11
Y4
CC
B3
A3
Y3
10
9
8
5
6
7
B2
Y2
GND
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
MC74HC00AN
N SUFFIX
14
AWLYYWWG
CASE 646
1
1
14
SOIC−14
HC00AG
14
D SUFFIX
AWLYWW
CASE 751A
1
1
14
TSSOP−14
14
DT SUFFIX
CASE 948G
ALYWG
1
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y
= Year
WW or W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC74HC00A/D
HC
00A
G

MC74HC00ANG Summary of contents

  • Page 1

    MC74HC00A Quad 2-Input NAND Gate High−Performance Silicon−Gate CMOS The MC74HC00A is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Capability: ...

  • Page 2

    ... Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

  • Page 3

    ... ORDERING INFORMATION Device MC74HC00AN MC74HC00ANG MC74HC00AD MC74HC00ADG MC74HC00ADR2 MC74HC00ADR2G MC74HC00ADTR2 MC74HC00ADTR2G MC74HC00AF MC74HC00AFG MC74HC00AFEL MC74HC00AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. ...

  • Page 4

    ... Maximum Low−Level Output OL Voltage I Maximum Input Leakage in Current I Maximum Quiescent Supply CC Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS ( pF, Input t L Symbol Parameter t , Maximum Propagation Delay, Input Output Y ...

  • Page 5

    INPUT 50 10% t PLH 90% OUTPUT Y 50% 10% t TLH Figure 1. Switching Waveforms OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 2. Test Circuit A B ...

  • Page 6

    −T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

  • Page 7

    ... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

  • Page 8

    ... S A −V− C 0.10 (0.004) −T− G SEATING D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...

  • Page 9

    ... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...