NJU26123V NJRC [New Japan Radio], NJU26123V Datasheet

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NJU26123V

Manufacturer Part Number
NJU26123V
Description
Digital Signal Processor for TV
Manufacturer
NJRC [New Japan Radio]
Datasheet

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- Software
- Hardware
Ver.2008-04-17
The NJU26123 is a high performance 24-bit digital signal processor.
The NJU26123 provides ‘NJRC Original Sound Enhancement’, ‘ Lip sync Audio
Delay’, 10band PEQ, HPF/LPF (FIR Filter), DRC, Tone Control, and Clipper.
These kinds of sound functions are suitable for TV, mini-component, CD
radio-cassette, speakers system and other audio products.
General Description
FEATURES
WatchDog Clock Output
NJRC Original Sound Enhancement (3D sound, Dialogue Boost, Bass Enhance )
Delay for Lip sync Audio Delay
10Band PEQ
HPF/LPF (FIR Filter)
DRC (Dynamic Range Compression) : 2-bands independent operation
Tone Control
Clipper
Master Volume
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
Digital Audio Interface
Digital Audio Format
Master / Slave Mode
Host Interface
Power Supply
Input terminal
Package
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
( fs=48kHz : Max. 36msec, fs=44.1kHz : Max. 39msec, fs=32kHz : Max. 54msec )
Digital Signal Processor for TV
: 3 Input ports / 3 Output ports
: I
: I
: 3.3V
: 5V Input tolerant
: SSOP24 (Pb-Free)
2
2
S 24bit, Left- justified, Right-justified, BCK : 32/64fs
C bus (Fast-mode/400kbps)
Package
NJU26123V
NJU26123
- 1 -

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NJU26123V Summary of contents

Page 1

... Digital Audio Format Master / Slave Mode - Master Mode, MCK : 384fs @32kHz, 256fs @48kHz Host Interface Power Supply Input terminal Package Ver.2008-04- Input ports / 3 Output ports 24bit, Left- justified, Right-justified, BCK : 32/64fs bus (Fast-mode/400kbps Input tolerant : SSOP24 (Pb-Free) NJU26123 ■ Package NJU26123V - 1 - ...

Page 2

NJU26123 ■ Function Block Diagram SCL INTERFACE SDA RESETb MCK TIMING CLKOUT GENERATOR / PLL CLK SLAVEb Internal Pow er (1.8V) Built-in LDO VREGO External Low -ESR 1.8V level terminal Capacitors Required - 2 - 24Bit Fixed-point ...

Page 3

DSP Block Diagram SDI0 SDI1 Input Trimmer SDI2 HPF EXEC Output LPF EXEC Output HPF Output SDO0/1/2 LPF Output Source Select PROC Output C/SW Output Ver.2008-04-17 Delay PEQ Tone Control SW1 SW4 (DRC enable / disable) DRC(HPF ...

Page 4

NJU26123 ■ Pin Configuration RESETb BCK 3 SDI2 4 SDI1 5 SDI0 6 MCK 7 VDD 8 VSS 9 STBYb 10 VSS 11 VREGO 12 ■ Pin Description Table 1 Pin Description No. Symbol I/O Description 1 ...

Page 5

Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Parameter Supply Voltage * Supply Voltage Bypass * In I/O, OD Pin Voltage * Out CLK CLKOUT Power Dissipation Operating Voltage Storage Temperature * The LSI must be used inside of ...

Page 6

NJU26123 ■ Electric Characteristics Table 3 Electric Characteristics Parameter *1 Operating Voltage Operating Current High Level Input Voltage Low Level Input Voltage *3 High Level Output Voltage Low Level Output Voltage *4 Leakage Current Clock Frequency *5 Clock Jitter Clock ...

Page 7

Power Supply, Input/Output terminal, Clock, Reset 1.1 Power Supply The NJU26123 has a power supply V should be implemented at the all power supply terminals. The NJU26123 include a built-in power supply (LDO) for internal logic. A built-in power ...

Page 8

NJU26123 1.4 Reset To initialize the NJU26123, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26123. After the power ...

Page 9

Digital Audio Clock Digital audio data needs to synchronize and transmit between digital audio systems. The NJU26123 - master mode / slave mode - both of the modes are supported Master mode; Use the clock of BCKO ...

Page 10

NJU26123 Table 6 Input clock (In Slave mode) Mode Clock Signal LR BCK (32fs) BCK (64fs) DSP MCK Slave (SLAVEb=”L”) MCK (SLAVEb=”H”) Table 7 Output clock (In Master mode) Mode Clock Signal LR DSP BCK (32fs) Master BCK (64fs) MCK ...

Page 11

Digital Audio Interface 3.1 Digital Audio Data Format The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format MSB is put on the 2nd bit of LR clock change ...

Page 12

NJU26123 The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format; ( (2) Left-Justified (3) Right-justified and 24bits data length. (Fig.6-1 to Fig6-12) An audio interface ...

Page 13

LRI, LRO BC KI LRI, LRO BCKI, BCKO ...

Page 14

NJU26123 3.3 Serial Audio Input Timing Table 10 Serial Audio Input Timing Parameters Parameter BCK Frequency * BCK Period * Low Pulse Width High Pulse Width BCK to LR Time ** LR to BCK Time ** Data Setup Time Data ...

Page 15

Host Interface The NJU26123 can be controlled via Serial Host Interface (SHI) using I packets (1 byte) when using either format. Refer to serial Host Interface Pin Description.(Table 12) Table 12 Serial Host Interface Pin Description Pin No. 16 ...

Page 16

NJU26123 2 Table bus Interface Timing Parameters Parameter SCL Clock Frequency Start Condition Hold Time SCL “Low” Duration SCL “High” Duration Start Condition Setup Time *1 Data Hole Time Data Setup Time Rising Time Falling Time Stop ...

Page 17

Pin setting The NJU26123 operates default command setting after resetting the NJU26123. In addition, the NJU26123 restricts operation at power on by setting PROC pin (No.17) (Table 15). This pin is input pin. However, this pin operates as bi-directional ...

Page 18

NJU26123 ■ NJU26123 Command Table Table 16 NJU26123 Command No. Command 1 Set Task 2 Fs Select 3 Smooth Control 4 Input Select 5 SDO0 Output Source Select 6 SDO1 Output Source Select 7 SDO2 Output Source Select 8 DRC ...

Page 19

Package SSOP24, Pb-Free Ver.2008-04-17 NJU26123 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages ...

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