NJU26126_10 NJRC [New Japan Radio], NJU26126_10 Datasheet

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NJU26126_10

Manufacturer Part Number
NJU26126_10
Description
Digital Signal Processor
Manufacturer
NJRC [New Japan Radio]
Datasheet
- Software
- Hardware
The NJU26126 is a high performance 24-bit digital signal processor.
The NJU26126 provides L/R channel independent 10bands PEQ, Low/High
bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio
Delay, eala & eala Rebirth of NJRC Original Sound Enhancement, Dynamic
Bass Boost, two systems Limiter, and 5.1 channel output function. These kinds
of sound functions are suitable for TV, mini-component, CD radio-cassette,
Sound bar and speakers system.
Ver.2010-08-19
General Description
FEATURES
Watchdog Clock Output
NJRC Original Sound Enhancement (eala, eala Rebirth, Dynamic Bass Boost )
HPF, LPF, Center/Sub woofer and Surround output function
10bands PEQ (Parametrical Equalizer) : L/R channel independent operation
DRC (Dynamic Range Compression) : 2-bands independent operation (FIR filter adoption)
Tone Control (Bass / Treble)
Limiter (SDO0 / SDO1)
Lip sync Audio Delay (fs=48kHz : Max. 22msec)
Signal level detector
24bit Fixed-point Digital Signal Processing
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
Digital Audio Interface
Digital Audio Format
Master / Slave Mode
Host Interface
Power Supply
Input terminal
Package
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
Digital Signal Processor
: 3 Input ports / 3 Output ports
: I
: I
: 3.3V
: 5V Input tolerant
: SSOP24-C2 (Pb-Free)
2
2
S 24bit, Left- justified, Right-justified, BCK : 32/64fs
C bus (Fast-mode/400kbps)
Package
NJU26126VC2
NJU26126
- 1 -

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NJU26126_10 Summary of contents

Page 1

General Description The NJU26126 is a high performance 24-bit digital signal processor. The NJU26126 provides L/R channel independent 10bands PEQ, Low/High bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio Delay, eala & eala Rebirth of ...

Page 2

NJU26126 ■ Function Block Diagram SCL INTERFACE SDA RESETb MCK TIMING CLKOUT GENERATOR / PLL CLK SLAVEb Internal Pow er (1.8V) Built-in LDO VREGO External Low -ESR 1.8V level terminal Capacitors Required ■ DSP Block Diagram SDI0 ...

Page 3

Pin Configuration RESETb BCK 3 SDI2 4 SDI1 5 SDI0 6 MCK 7 VDD 8 VSS 9 STBYb 10 VSS 11 VREGO 12 ■ Pin Description Table 1 Pin Description No. Symbol I/O Description 1 RESETb ...

Page 4

NJU26126 ■ Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Parameter Supply Voltage * Supply Voltage Bypass * In I/O, OD Pin Voltage * Out CLK CLKOUT Power Dissipation Operating Voltage Storage Temperature * The LSI must be used inside ...

Page 5

Electric Characteristics Table 3 Electric Characteristics Parameter *1 Operating Voltage Operating Current High Level Input Voltage Low Level Input Voltage *3 High Level Output Voltage Low Level Output Voltage *4 Leakage Current Clock Frequency *5 Clock Jitter Clock Duty ...

Page 6

NJU26126 1. Power Supply, Input/Output terminal, Clock, Reset 1.1 Power Supply The NJU26126 has a power supply V should be implemented at the all power supply terminals. The NJU26126 include a built-in power supply (LDO) for internal logic. A built-in ...

Page 7

Reset To initialize the NJU26126, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26126. After the power supply ...

Page 8

NJU26126 2. Digital Audio Clock Digital audio data needs to synchronize and transmit between digital audio systems. The NJU26126 - master mode / slave mode - both of the modes are supported Master mode; Use the clock of ...

Page 9

Table 6 Input clock (In Slave mode) Mode Clock Signal LR BCK (32fs) BCK (64fs) DSP MCK Slave (SLAVEb=”L”) MCK (SLAVEb=”H”) Table 7 Output clock (In Master mode) Mode Clock Signal LR DSP BCK (32fs) Master BCK (64fs) MCK Ver.2010-08-19 ...

Page 10

NJU26126 3. Digital Audio Interface 3.1 Digital Audio Data Format The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format MSB is put on the 2nd bit of LR clock ...

Page 11

The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format; ( (2) Left-Justified (3) Right-justified and 24bits data length. (Fig.6-1 to Fig6-12) An audio interface input ...

Page 12

NJU26126 LRI, LRO BC KI LRI, LRO BCKI, BCKO ...

Page 13

Serial Audio Input Timing Table 10 Serial Audio Input Timing Parameters Parameter BCK Frequency * BCK Period * Low Pulse Width High Pulse Width BCK to LR Time ** LR to BCK Time ** Data Setup Time Data Hold ...

Page 14

NJU26126 ■ Host Interface The NJU26126 can be controlled via Serial Host Interface (SHI) using I packets (1 byte) when using either format. Refer to serial Host Interface Pin Description.(Table 12) Table 12 Serial Host Interface Pin Description Pin No. ...

Page 15

Table bus Interface Timing Parameters Parameter SCL Clock Frequency Start Condition Hold Time SCL “Low” Duration SCL “High” Duration Start Condition Setup Time *1 Data Hole Time Data Setup Time Rising Time Falling Time Stop Condition ...

Page 16

NJU26126 ■ Pin setting The NJU26126 operates default command setting after resetting the NJU26126. In addition, the NJU26126 restricts operation at power on by setting PROC pin (No.17) (Table 15). This pin is input pin. However, this pin operates as ...

Page 17

NJU26126 Command Table Table 16 NJU26126 Command No. Command 1 Set Task 2 Fs Select 3 Smooth Control setup 4 Input Select 5 SDO0 output source select 6 SDO1 output source select 7 SDO2 output source select 8 DRC ...

Page 18

NJU26126 ■ Package SSOP24-C2, Pb-Free - 18 - [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show ...

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