cxa2027q Sony Electronics, cxa2027q Datasheet - Page 14

• Manufacturer Part Number: cxa2027q
• Description: Analog Signal Processor Ic
• Manufacturer: Sony Electronics

Notes on Operation
1. Pre-stage GCA
2. Post-stage GCA
3. Line clamp
4. Pixel clamp
5. DC offset adjustment between channels
6. Output DC voltage adjustment
7. Pulse input signals
The gain characteristics is as given in page 16. As a guideline, the calculation formula is 0.5
(n = 0 to 31: n is D/A converter input in decimal).
The gain characteristics is as given in page 16. When the GC pin is open, gain becomes approximately
double.
When the LCLP pulse (line clamp pulse) is made high during the optical black period of CCD output, output
(Pin 20) is clamped approximately to VRB (= 2.0V) voltage.
The pixel clamp function (at Pins 35, 36 and 37) requires large charging and discharging current through
the capacitor, therefore, keep the ground area below the emitter follower as wide as possible. The distance
between the input capacitor and input pin should also be as short as possible.
There is a slight difference between clamp voltages (black level voltage) of different channels due to
component scatterings within the IC. Correct the B and G channel DC levels relative to R channel using
D4-0 to D4-4 and D5-0 to D5-4. The adjustment step for the input pins (Pins 36 and 37) is approximately
5mV/LSB. The standard settings are D4-0 to D4-3 = “L”, D4-4 = “H”, and D5-0 to D5-3 = “L”, D5-4 = “H”.
Output (Pin 20) clamp voltage varies slightly due to variations within the IC. Adjust output clamp voltage
using D6-0 to D6-5. The adjustment step is approximately 1mV/LSB. The standard settings are D6-0, D6-1
= “H”, D6-2 to D6-5 = “L”.
Sharp edges at input pulse signals may affect output. If there is a problem, insert a damping resistor
(around 100 to 200 ) to smooth the pulse’s edges.
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