cxd1217q Sony Electronics, cxd1217q Datasheet - Page 5

• Manufacturer Part Number: cxd1217q
• Description: Synchronizing Signal Generator For Video Camera
• Manufacturer: Sony Electronics

Description of Operation (See Block Diagram.)
The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them,
the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted .
As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the
PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL.
1 . MODE specified input
The CXD1217 provides four inputs to specify the respective modes.
2. Reset operation
The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation
when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC
internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched
as a reset operation to each other (GEN Iocked).
• H reset (HRI input)
TEST input: An input to be used to measure IC. This input is normally kept opened.
When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge,
and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns)
against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed.
The minimum resetting pulse width is over 0.3µs.
The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit
shown in the diagram below.
EXT input: Set this pin to V
MODE1 and MODE2 inputs: These are inputs for the system selection.
SECAM
NTSC
PALM
PAL
MODE1
0
0
1
1
counters in connection with the PLL Ioop as shown in the upper part of the block diagram
become into stand still state.
(Because it is dropped internally to Vss with MOS resistance.)
4fsc = 1135f
HRI input
CXD1217
HD OUT output
4fsc = 910f
4fsc = 909f
Sub carrier
—
H
MODE2
+ 2fv
H
H
0
1
0
1
DD
side, and it becomes into external synchronizing mode. At this time, the
Reset
Clock
910f
908f
910f
908f
H
H
H
H
SECAM
System
NTSC
PALM
PAL
– 5 –
"0"
"1"
6.3 to 6.37 [µs]
V
V
SS
DD
70ns) than the HRI input as
CXD1217Q