lc7940kd Sanyo Semiconductor Corporation, lc7940kd Datasheet - Page 5

• Manufacturer Part Number: lc7940kd
• Description: Stn Dot Matrix Lcd Segment Driver
• Manufacturer: Sanyo Semiconductor Corporation

Pin Function
LC7940KD
1 to 80
100
91
86
87
92
89
88
99
98
97
96
95
94
93
85
82
84
81
83
90
Pin No
LC7941KDR
80 to 1
100
90
95
94
89
92
93
81
82
83
84
85
86
87
88
96
99
97
91
98
O1 to O80
DISPOFF
Symbol
LOAD
CDO
V DD
V SS
V EE
CDI
SDI
P/S
DI3
DI2
DI1
NC
NC
NC
CP
V1
V3
V4
M
Supply
Supply
LC7940KD / LC7941KDR
I/O
O
O
I
I
I
I
I
I
I
I
I
I
-
LCD panel drive voltage supplies
V DD -V SS is the logic supply.
V DD -V EE is the LCD supply.
LCD panel drive voltage supplies
V1 and V EE are selected levels.
V3 and V4 are not-selected levels.
Chip disable.
Data is read in When LOW, and not read in When HIGH.
On the falling edge, the LCD drive signals set by the display data are output.
4-bit parallel data input pins.
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
LCD panel drive voltage output alternation control signal.
Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW.
Data is read out when HIGH. Goes LOW after data is read out.
Connected to the CDI input of the next chip.
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISPOFF input
as shown below.
Note* don’t care (tied HIGH or LOW)
O1 to O80 output control input pin.
When LOW, V1 is output on the O1 to O80 outputs.
See the truth table.
No connection.
Display data input clock (falling edge trigger).
Display data latch clock (falling edge trigger).
Serial data input.
Cascade connection pin for extension segment drivers.
Data input
SDI
DI3
DI2
DI1
M
H
H
L
L
*
O4
O3
O2
O1
Q
H
H
L
L
*
Function
O8
O7
O6
O5
LCD driver output
DISPOFF
H
H
H
H
L
→
Output
No.A0573-5/13
V EE
V3
V1
V1
V4
O80
O79
O78
O77