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Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Bt829B/827B VideoStreamII Decoders Bt829B– Video Capture Processor and Scaler for TV/VCR Analog Input Bt827B– Composite Video and S-Video ...
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... Ordering Information Model Number Bt829BKRF Bt827BKRF Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: March 1998 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 1.8 Video Adjustments 1.8.1 The Hue Adjust Register (HUE ...
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Bt829B/827B VideoStream II Decoders 3.0 PC Board Layout Considerations 3.1 Ground Planes 3.1.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.0 Parametric Information 5.1 DC Electrical Parameters 5.2 AC Electrical Parameters 5.3 Package Mechanical Drawings 5.4 Revision History ...
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Bt829B/827B VideoStream II Decoders List of Figures Figure 1-1. Bt829B/827B Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 2-7. YCrCb 4:2:2 Pixel Stream Format (SPI Mode, 8- and 16-Bits Figure 2-8. Bt829B/827B ...
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Bt829B/827B VideoStream II Decoders List of Tables Table 1-1. VideoStream II Features Options . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables x D829BDSA Bt829B/827B VideoStream II Decoders ...
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Functional Description 1.1 Functional Overview Rockwell’s VideoStream II products are a family of single-chip, pin-and register- compatible solutions for processing analog NTSC/PAL/SECAM video into digi- tal 4:2:2 YCrCb video. They provide a comprehensive choice of capabilities to enable the ...
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Functional Description 1.1 Functional Overview Figure 1-1. Bt829B/827B Detailed Block Diagram AGC and Sync Detect JTAG A/D A/D Oversampling Low-Pass Filter Y/C Separation Chroma Demod Hue, Saturation, and Brightness Adjust Horizontal and Vertical Filtering and Scaling ...
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Bt829B/827B VideoStream II Decoders 1.1.1 Bt829B Video Capture Processor for TV/VCR Analog Input The Bt829B Video Capture Processor is a fully integrated single-chip decoding and scaling solution for analog NTSC/PAL/SECAM input signals from TV tun- ers, VCRs, cameras, and other ...
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Functional Description 1.1 Functional Overview 1.1.3 Bt829B Architecture and Partitioning The Bt829B has been developed to provide the most cost-effective, high-quality video input solution used for low-cost multimedia subsystems that integrate both graphics display and video capabilities. ...
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Bt829B/827B VideoStream II Decoders 1.1.5 Scaling and Cropping The Bt829B can reduce the video image size in both horizontal and vertical direc- tions independently using arbitrarily selected scaling ratios. The X and Y dimen- sions can be scaled down to ...
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Functional Description 1.1 Functional Overview 1.1.8 VBI Data Pass-Through The Bt829B/827B provides VBI data passthrough capability. The VBI region ancillary data is captured by the video decoder and made available to the system for subsequent software processing. The Bt829B/827B ...
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Bt829B/827B VideoStream II Decoders 1.2 Pin Descriptions Figure 1-2 details the Bt829B and Bt827B pinout. Table 1-2 provides pin numbers, names, input and output functions, and descriptions. Figure 1-2. Bt829B/827B Pinout Diagram 1 VDDO 2 VD[15] 3 VD[14] 4 VD[13] ...
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Functional Description 1.2 Pin Descriptions Table 1-2. Pin Descriptions Grouped By Pin Function ( Pin # I/O Pin Name 45, 50, 55, I MUX[3: MUXOUT 52 I YIN 67 I CIN 59 I SYNCDET ...
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Bt829B/827B VideoStream II Decoders Table 1-2. Pin Descriptions Grouped By Pin Function ( Pin # I/O Pin Name 82 O HRESET 79 O VRESET 83 O ACTIVE 94 O QCLK FIELD 89 O ...
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Functional Description 1.2 Pin Descriptions Table 1-2. Pin Descriptions Grouped By Pin Function ( Pin # I/O Pin Name 91 I PWRDN 86 O VACTIVE 85 I OEPOLE 12 A XT0I 13 A XT0O 16 A XT1I ...
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Bt829B/827B VideoStream II Decoders Table 1-2. Pin Descriptions Grouped By Pin Function ( Pin # I/O Pin Name 35 I TRST 10, 38, 76, P VDD + 20, 30 VDDO + 3.3 ...
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Functional Description 1.3 Differences Between Bt829A/827A and Bt829B/827B 1.3 Differences Between Bt829A/827A While both Bt829A/827A and Bt829B/827B video decoders are pin and software compatible, please note the differences, as described in Table 1-3. A 3.3 V mode has been ...
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Bt829B/827B VideoStream II Decoders The pins shown in Table 1-5 can receive 3.3 V signal levels when pins 1, 20, 30, and 92 (VDDO) are connected to a 3.3 V power supply: Table 1-5. 3.3 V Pin Input When using ...
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Functional Description 1.4 UltraLock 1.4 UltraLock 1.4.1 The Challenge The line length (the interval between the midpoints of the falling edges of suc- ceeding horizontal sync pulses) of analog video sources is not constant. For a sta- ble source ...
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Bt829B/827B VideoStream II Decoders Figure 1-3. UltraLock Behavior for NTSC Square Pixel Output Analog Waveform Length Per Line Sent to the FIFO Ultralock UltraLock can be used to extract any programmable number of pixels from the original video stream as ...
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Functional Description 1.5 Composite Video Input Formats 1.5 Composite Video Input Formats The Bt829B supports several composite video input formats. Table 1-6 specifies the different video formats and some of the countries in which each format is used. Table ...
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Bt829B/827B VideoStream II Decoders The video decoder must be programmed appropriately for each of the composite video input formats. Table 1-7 lists the register values that need to be programmed for each input format. Table 1-7. Register Values for Video ...
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Functional Description 1.6 Y/C Separation and Chroma Demodulation 1.6 Y/C Separation and Chroma Demodulation Y/C separation and chroma decoding is illustrated in Figure 1-4. Bandpass and notch filters are implemented to separate the composite video stream. Figure 1-5 displays ...
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Bt829B/827B VideoStream II Decoders Figure 1-6 schematically describes the filtering and scaling operations. In addition to the Y/C separation and chroma demodulation illustrated in Figure 1-4, the Bt829B also supports chrominance comb filtering as an optional filtering stage after chroma ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation 1.7 Video Scaling, Cropping, and Temporal The Bt829B provides three mechanisms to reduce the amount of video pixel data in its output stream: down-scaling, cropping, and temporal decimation. All three ...
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Bt829B/827B VideoStream II Decoders Figure 1-8. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC) QCIF ICON CIF Figure 1-9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM) CIF QCIF ICON The Bt829B implements horizontal ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation Figure 1-10. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters Figure 1-11. Combined Luma Notch and 2x Oversampling Filter Response 22 2-tap 3-tap 4-tap 5-tap PAL/SECAM NTSC D829BDSA ...
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Bt829B/827B VideoStream II Decoders 1.7.3 Peaking The Bt829B enables four different peaking levels by programming the PEAK bit and HFILT bits in the SCLOOP register. The filters are shown in Figures 1-12 and 1-13. Figure 1-12. Peaking Filters 1.7 Video ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation Figure 1-13. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch The number of taps in the vertical filter is set by the VTC register. The user may select ...
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Bt829B/827B VideoStream II Decoders 1.7.4 Chrominance Scaling A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chromi- nance. Vertical scaling of chrominance is implemented through chrominance comb filtering using a line store, followed by simple decimation or line ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation In this equation, the HACTIVE value cannot be cropped; it represents the total active region of the video line. This equation produces roughly the same result as using the full ...
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Bt829B/827B VideoStream II Decoders Vertical Scaling Ratio Register (VSCALE) vertical scaling ratio. It defines the number of vertical lines output by the Bt829B. The following formula should be used to determine the value to be entered into this 13-bit register. ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation where: If your target machine has sufficient memory to statically store the scaling values locally, the READ operation can be eliminated. On vertical scaling (when scaling below CIF resolution) it ...
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Bt829B/827B VideoStream II Decoders Figure 1-14. Effect of the Cropping and Active Registers Video Frame Video Frame 1.7 Video Scaling, Cropping, and Temporal Decimation Cropped image HDELAY HACTIVE Cropped Image HDELAY HACTIVE Falling Edge of HRESET D829BDSA 1.0 Functional Description ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation 1.7.7 Cropping Registers Horizontal Delay Register (HDELAY) between the falling edge of HRESET and the rising edge of ACTIVE. The count is programmed with respect to the scaled frequency clock. ...
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Bt829B/827B VideoStream II Decoders When cropping is not implemented, the number of clocks at the 4x sample rate (the CLKx1 rate) in each of these regions is as follows: PAL/SECAM The value for HDELAY is calculated using the following formula: ...
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Functional Description 1.7 Video Scaling, Cropping, and Temporal Decimation 1.7.8 Temporal Decimation Temporal decimation provides a solution for video synchronization during peri- ods when full frame rate cannot be supported due to bandwidth and system restrictions. For example, when ...
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Bt829B/827B VideoStream II Decoders 1.8 Video Adjustments The Bt829B provides programmable hue, contrast, saturation, and brightness. 1.8.1 The Hue Adjust Register (HUE) The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC, the hue ...
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Functional Description 1.9 Bt829B VBI Data Output Interface 1.9 Bt829B VBI Data Output Interface 1.9.1 Introduction A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM. Figure 1-16 illustrates an NTSC video frame in ...
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Bt829B/827B VideoStream II Decoders The Bt829B can be configured in a mode known as VBI data pass through to enable capture of the VBI region ancillary data for later processing by software. In this mode the VBI region of the ...
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Functional Description 1.9 Bt829B VBI Data Output Interface 1.9.3 Functional Description There are three modes of operation for the Bt829B VBI data pass-through feature 1.9.4 VBI Line Output Mode The VBI line output mode is enabled ...
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Bt829B/827B VideoStream II Decoders The VBI data sample stream which is output during the VBI horizontal active period represents an 8*Fsc sampled version of the analog video signal starting in the vicinity of the subcarrier burst and ending after the ...
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Functional Description 1.9 Bt829B VBI Data Output Interface Figure 1-21. Location of VBI Data VRESET HRESET HACTIVE VACTIVE DVALID VD[15:0] VRESET HRESET HACTIVE VACTIVE DVALID VD[15:0] 38 Odd Field VBI Data VBI Data VBI Data Invalid Data YCrCb Data ...
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Bt829B/827B VideoStream II Decoders The Bt829B can provide VBI data in all the pixel port output configurations (i.e., 16-bit SPI, 8-bit SPI, and ByteStream modes). The range of the VBI data can be controlled with the RANGE bit in the ...
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Functional Description 1.9 Bt829B VBI Data Output Interface 1.9.5 VBI Frame Output Mode In VBI frame output mode, the Bt829B is generating VBI data all the time (i.e., there is no VBI active interval). In essence, the Bt829B is ...
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Bt829B/827B VideoStream II Decoders 1.10 Closed Captioning and Extended Data In a system capable of capturing Closed Captioning and Extended Data Services adhering to the EIA-608 standard, 2 bytes of information are presented to the video decoder on line 21 ...
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Functional Description 1.10 Closed Captioning and Extended Data Services Decoding The Bt829B provides location FIFO for storing CC/EDS data. Once the video decoder detects the start signal in the CC/EDS signal, it captures the low ...
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Bt829B/827B VideoStream II Decoders When the first byte of CC/EDS data is decoded and stored in the FIFO, the data is immediately placed in the CC_DATA and CC_STATUS registers and is available to be read. Once the data is read ...
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Functional Description 1.10 Closed Captioning and Extended Data Services Decoding 1.10.3 Coring The Bt829B video decoder can perform a coring function, in which it forces all values below a programmed level to be zero. This is useful because the ...
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Electrical Interfaces 2.1 Input Interface 2.1.1 Analog Signal Selection The Bt829B/827B contains an on-chip 4:1 MUX. For the Bt829B and Bt827B, this multiplexer can be used to switch between four composite sources or three composite sources and one S-Video ...
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Electrical Interfaces 2.1 Input Interface 2.1.3 Autodetection of NTSC or PAL/SECAM Video If the Bt829B is configured to decode both NTSC and PAL/SECAM, the Bt829B can be programmed to automatically detect which format is being input to the chip. ...
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Bt829B/827B VideoStream II Decoders 2.1.7 Automatic Gain Controls (AGC) The REFOUT, CREF+, and YREF+ pins should be connected together as shown in Figure 2-1. In this configuration, the Bt829B controls the voltage for the top of the reference ladder for ...
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Electrical Interfaces 2.1 Input Interface Figure 2-1. Bt829B Typical External Circuitry with Third Overtone Crystal Oscillators (5 V VDD) REFOUT YREF+ CREF+ 0.1 F CLEVEL 0.1 F YREF– CREF– 1.0 F MUX0 75 1.0 F MUX1 75 1.0 F ...
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Bt829B/827B VideoStream II Decoders Figure 2-2. Bt829B Typical External Circuitry with Third Overtone Crystal Oscillators (3.3V VDDO) REFOUT YREF+ CREF+ 0.1 F CLEVEL 0.1 F YREF– CREF– 1.0 F MUX0 75 1.0 F MUX1 75 1.0 F MUX2 75 1.0 ...
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Electrical Interfaces 2.1 Input Interface 2.1.8 Crystal Inputs and Clock Generation The Bt829B has two pairs of pins: XT0I/XT0O and XT1I/XT1O. They are used to input a clock source. If both NTSC and PAL video are being digitized, both ...
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Bt829B/827B VideoStream II Decoders The clock source tolerance should be 50 ppm or less, but 100 ppm is accept- able. Devices that output CMOS voltage levels are required. The load capacitance in the crystal configurations may vary, depending on the ...
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Electrical Interfaces 2.1 Input Interface Figure 2-3. Clock Options (3.3 V VDD) 28.63636 MHz 2.7 H 100 pF NTSC Third Overtone Mode Crystal Oscillator Osc 28.63636 MHz NTSC Single-Ended Oscillator 28.63636 MHz ...
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Bt829B/827B VideoStream II Decoders Figure 2-4. Clock Options (5 V VDD) 28.63636 MHz 0.1 F 2.7 H NTSC Third Overtone Mode Crystal Oscillator Osc 28.63636 MHz NTSC Single-Ended Oscillator 28.63636 MHz ...
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Electrical Interfaces 2.1 Input Interface 2.1.9 2X Oversampling and Input Filtering To avoid aliasing artifacts, digitized video needs to be band-limited. Because the Bt829B samples at CLKx2 (8xFsc—more than twice the normal rate), no filtering is required at the ...
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Bt829B/827B VideoStream II Decoders 2.2 Output Interface 2.2.1 Output Interfaces The Bt829B supports a Synchronous Pixel Interface (SPI). SPI can support 8-bit or 16-bit YCrCb 4:2:2 data streams. Bt829B outputs all pixel and control data synchronous with CLKx1 (16-bit mode), ...
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Electrical Interfaces 2.2 Output Interface 2.2.2 YCrCb Pixel Stream Format, SPI Mode, 8- and 16-Bit Formats When the output is configured for an 8-bit pixel interface, the data is output on pins VD[15:8]. Eight bits of chrominance data precede ...
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Bt829B/827B VideoStream II Decoders 2.2.3 Synchronous Pixel Interface (SPI Mode 1) Upon reset, the Bt829B initializes to the SPI output, Mode 1 (SPI-1). In this mode, Bt829B outputs all horizontal and vertical blanking interval pixels, in addi- tion to the ...
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Electrical Interfaces 2.2 Output Interface 2.2.4 Synchronous Pixel Interface (SPI Mode 2, ByteStream) In SPI Mode 2, the Bt829B encodes all video timing control signals onto the pixel data bus. ByteStream is the 8-bit version of this configuration. Because ...
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Bt829B/827B VideoStream II Decoders Table 2-2. Description of the Control Codes in the Pixel Stream Luma Value 0x03 0x04 0x05 0x06 Figure 2-10. Data Output in SPI Mode 2 (ByteStream) CLKx2 HRESET: beginning of horizontal line during vertical blanking VD(15:8) ...
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Electrical Interfaces 2.2 Output Interface Figure 2-11. Video Timing in SPI Modes 1 and 2 HRESET VRESET FIELD ACTIVE HRESET VRESET FIELD ACTIVE Notes: (1). HRESET precedes VRESET by two clock cycles at the beginning of fields 1, 3, ...
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Bt829B/827B VideoStream II Decoders Figure 2-12. Horizontal Timing Signals in the SPI Modes HRESET ACTIVE Table 2-3. Data Output Ranges 2.2.5 CCIR601 Compliance When the RANGE bit is set to zero, the output levels are fully compliant with the CCIR601 ...
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Electrical Interfaces 2 2 Interface 2.3 I The Inter-Integrated Circuit bus is a two-wire serial interface. Serial Clock (SCL) and Data Lines (SDA) are used to transfer data between the bus master and the slave device. The ...
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Bt829B/827B VideoStream II Decoders 2.3.2 Addressing the Bt829B An I R/W command. The R/W bit is appended to the base address to form the transmit- ted I Figure 2-14. I Table 2-4. Bt829B Address Matrix 2.3.3 Reading and Writing After ...
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Electrical Interfaces 2 2 Interface To stop a read transfer, the host must not acknowledge the last read cycle. The Bt829B then releases the data bus in preparation for a stop command acknowledgment is received, ...
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Bt829B/827B VideoStream II Decoders 2 Table 2-5. Example I C Data Transactions Data Master Bt829B Flow 2 —— Start > ACK <— Data(0) — ACK(0) . <— — <— . — <— — <— ...
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Electrical Interfaces 2 2 Interface 2 Figure 2-15 Protocol Diagram Data Write S CHIP ADDR A SUB-ADDR 0x88 or 0x8A 8 Bits Data Read S CHIP ADDR A DATA A 0x89 or 0x8B Write Followed ...
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Bt829B/827B VideoStream II Decoders 2.4 JTAG Interface 2.4.1 Need for Functional Verification As the complexity of imaging chips increases, the need to easily access individual chips for functional verification is vital. The Bt829B incorporates special circuitry which makes it accessible ...
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Electrical Interfaces 2.4 JTAG Interface 2.4.3 Optional Device ID Register The Bt829B has the optional device identification register defined by the JTAG specification. This register contains information concerning the revision, actual part number, and manufacturer’s identification code that is ...
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Bt829B/827B VideoStream II Decoders 2.4.5 Example BSDL Listing attribute BOUNDARY_REGISTER of Bt829B : entity is “ 0 (BC_1, *, control, 1),” & “ 1 (BC_1, *, internal, 1),” & “ 2 (BC_1, *, control, 1),” & “ 3 (BC_1, *, ...
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Electrical Interfaces 2.4 JTAG Interface 70 “ 38 (BC_1, CBFLAG, output3, X, 28, 0, Z),” & “ 39 (BC_3, NVSEN, input, X),” & “ 40 (BC_1, PWRDN, input, X),” & “ 41 (BC_1, QCLK, output3, X, 28, 0, Z),” ...
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Bt829B/827B VideoStream II Decoders “ 78 (BC_1, TWREN, input, X),” & “ 79 (BC_0, *, internal, 0),” & “ 80 (BC_0, *, internal, 0)”; end Bt829B; D829BDSA 2.0 Electrical Interfaces 2.4 JTAG Interface 71 ...
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Electrical Interfaces 2.4 JTAG Interface 72 D829BDSA Bt829B/827B VideoStream II Decoders ...
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PC Board Layout Considerations The layout should be optimized for lowest noise on the Bt829B power and ground lines. Optimization is achieved by shielding the digital inputs and outputs and by providing good decoupling. The lead length between groups ...
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PC Board Layout Considerations 3.1 Ground Planes 3.1.1 Power Planes The power plane area should encompass all Bt829B power pins, voltage reference circuitry, power supply bypass circuitry for the Bt829B, analog input traces, any input amplifiers, and all the ...
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Bt829B/827B VideoStream II Decoders 3.1.2 Supply Decoupling The bypass capacitors should be installed with the shortest leads possible (consis- tent with reliable operation) to reduce the lead inductance. These capacitors should be placed as close as possible to the device. ...
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PC Board Layout Considerations 3.1 Ground Planes Figure 3-4. Typical Power and Ground Connection Diagram and Parts List for 3.3 V I/O Mode +3 (VCC Ground Location (1) 0.1 F ceramic capacitor C1, C2 ...
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Bt829B/827B VideoStream II Decoders 3.1.3 Digital Signal Interconnect The digital signals of the Bt829B should be isolated as much as possible from the analog signals and other analog circuitry. Also, the digital signals should not over- lay the analog power ...
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PC Board Layout Considerations 3.1 Ground Planes 78 D829BDSA Bt829B/827B VideoStream II Decoders ...
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Control Register Definitions This section describes the function of the various control registers in detail. Table 4-1 summarizes the register functions. Table 4-1. Register Map ( Register Name Mnemonic Device Status STATUS Input Format IFORM Temporal Decimation ...
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Control Register Definitions Table 4-1. Register Map ( Register Name Mnemonic Hue Control HUE SC Loop Control SCLOOP White Crush Up Count WC_UP Output Format OFORM Vertical Scaling, VSCALE_HI Upper Byte Vertical Scaling, VSCALE_LO Lower Byte Test ...
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Bt829B VideoStream II Decoders 0x00—Device Status Register (STATUS) \The MPU can read or write to this register at any time. Upon reset initialized to 0x00. COF is the LSB. By writing to the register, the COF and LOF ...
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Control Register Definitions 0x01—Input Format Register (IFORM) Luma ADC Overflow—On power-up, this bit is set ADC overflow occurs, the bit is LOF set to a logical reset after being written to, or ...
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Bt829B VideoStream II Decoders 0x02—Temporal Decimation Register (TDEC) The MPU can read or write to this control register at any time. Upon reset initialized to 0x00. DEC_RAT(0) is the LSB. This register enables temporal decimation by discarding a ...
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Control Register Definitions 0x04—Vertical Delay Register, Lower Byte (VDELAY_LO) 0x04—Vertical Delay Register, Lower Byte (VDELAY_LO) The MPU can read or write to this control register at any time. Upon reset initialized to 0x16. The LSB (LSB) is ...
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Bt829B VideoStream II Decoders 0x07—Horizontal Active Register, Lower Byte (HACTIVE_LO) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x80. HACTIVE_LO(0) is the LSB. HACTIVE defines the number ...
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Control Register Definitions 0x0A—Brightness Control Register (BRIGHT) 0x0A—Brightness Control Register (BRIGHT) The brightness control involves the addition of a two’s complement number to the luma channel. Brightness can be adjusted in 255 steps, from –128 to +127. The resolution ...
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Bt829B VideoStream II Decoders 0x0B—Miscellaneous Control Register (CONTROL) The MPU can read or write to this control register at any time. Upon reset initialized to 0x20. SAT_V_MSB is the LSB. An asterisk indicates the default option ...
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Control Register Definitions 0x0C—Luma Gain Register, Lower Byte (CONTRAST_LO) 0x0C—Luma Gain Register, Lower Byte (CONTRAST_LO) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0xD8. CONTRAST_LO(0) is ...
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Bt829B VideoStream II Decoders 0x0D—Chroma (U) Gain Register, Lower Byte (SAT_U_LO) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0xFE. SAT_U_LO(0) is the LSB. SAT_U_MSB in the ...
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Control Register Definitions 0x0E—Chroma (V) Gain Register, Lower Byte (SAT_V_LO) 0x0E—Chroma (V) Gain Register, Lower Byte (SAT_V_LO) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0xB4. ...
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Bt829B VideoStream II Decoders 0x0F—Hue Control Register (HUE) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x00. HUE(0) is the LSB. Hue adjustment involves the addition of ...
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Control Register Definitions 0x10—SC Loop Control (SCLOOP) 0x10—SC Loop Control (SCLOOP) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x00. ACCEL is the LSB. An asterisk ...
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Bt829B VideoStream II Decoders 0x11—White Crush Up Count Register (WC_UP) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0xCF. UPCNT(0) is the LSB MAJS 1 ...
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Control Register Definitions 0x12—Output Format Register (OFORM) 0x12—Output Format Register (OFORM) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x06. OES(0) is the LSB. An asterisk ...
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Bt829B VideoStream II Decoders OES[1] and OES[0] control the output three-states when the OE pin or the OUTEN bit OES (VPOLE bit 7) is asserted. The pins are divided into three groups: timing (HRESET, VRESET, ACTIVE, VACTIVE, CBFLAG, DVALID, and ...
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Control Register Definitions 0x14—Vertical Scaling Register, Lower Byte (VSCALE_LO) 0x14—Vertical Scaling Register, Lower Byte (VSCALE_LO) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x00 ...
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Bt829B VideoStream II Decoders 0x16—Video Timing Polarity Register (VPOLE) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x00. An asterisk indicates the default option OUT_EN ...
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Control Register Definitions 0x17—ID Code Register (IDCODE) 0x17—ID Code Register (IDCODE) This control register may be read by the MPU at any time. PART_REV(0) is the LSB PART_ID 1 1 PART_ID PART_REV 0x0 – 0xF = Current ...
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Bt829B VideoStream II Decoders 0x19—Burst Delay Register (BDELAY) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x5D. BDELAY(0) is the LSB This register ...
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Control Register Definitions 0x1A—ADC Interface Register (ADC) 0x1A—ADC Interface Register (ADC) This control register may be written to or read by the MPU at any time. Upon reset initialized to 0x82. Reserved is the LSB. An asterisk ...
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Bt829B VideoStream II Decoders 0x1B—Video Timing Control (VTC) This register may be written to or read by the MPU at any time. Upon reset initialized to 0x00. VFILT(0) is the LSB. An asterisk indicates the default option. 7 ...
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Control Register Definitions 0x1B—Video Timing Control (VTC) These bits control the number of taps in the Vertical Scaling Filter. The number of taps must be VFILT chosen in conjunction with the horizontal scale factor to ensure that the needed ...
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Bt829B VideoStream II Decoders 0x1C—Extended Data Service/Closed Caption Status Register (CC_STATUS) This register may be written or read by the MPU at any time. Upon reset, the value of register bits 7, 1, and 0 are indeterminate because their status ...
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Control Register Definitions 0x1D—Extended Data Service/Closed Caption Data Register 0x1D—Extended Data Service/Closed Caption Data Register (CC_DATA) The CC-DATA register is read only and can be read by the MPU at any time. Any writes to this register are ignored. ...
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Bt829B VideoStream II Decoders 0x3F—Programmable I/O Register (P_IO) This control register may be written to or read by the MPU at any time. Upon reset, the value of the register bits is initialized to 0x00. OUT_0 is the LSB. While ...
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Control Register Definitions 0x3F—Programmable I/O Register (P_IO) 106 D829BDSA Bt829B VideoStream II Decoders ...
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Parametric Information 5.1 DC Electrical Parameters Table 5-1. Recommended Operating Conditions Parameter Power Supply — Analog Power Supply — 5.0 V Digital Power Supply — 3.3 V Digital Maximum |V – MUX0, MUX1 and MUX2 ...
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Parametric Information 5.1 DC Electrical Parameters Table 5-2. Absolute Maximum Ratings Parameter V (measured to AGND (measured to DGND) DD Voltage on any signal pin (See the note below) Analog Input Voltage Storage Temperature Junction Temperature Vapor ...
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Bt829B/827B VideoStream II Decoders Table 5-4. DC Characteristics (5 V only operation) Parameter Digital Inputs Input High Voltage (TTL) Input Low Voltage (TTL) Input High Voltage (XT0I, XT1I,) Input Low Voltage (XT0I, XT1I,) Input High Current ( ...
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Parametric Information 5.2 AC Electrical Parameters 5.2 AC Electrical Parameters Table 5-5. Clock Timing Parameters ( Parameter NTSC: CLKx1 Rate CLKx2 Rate (50 PPM source required) PAL/SECAM: CLKx1 Rate CLKx2 Rate (50 PPM source required) XT0 and ...
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Bt829B/827B VideoStream II Decoders Table 5-5. Clock Timing Parameters ( Parameter CLKx1 Duty Cycle CLKx2 Duty Cycle CLKx2 to CLKx1 Delay CLKx1 to Data Delay CLKx2 to Data Delay CLKx1 (Falling Edge) to QCLK (Rising Edge) CLKx2 (Falling ...
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Parametric Information 5.2 AC Electrical Parameters Figure 5-1. Clock Timing Diagram XT0I or XT1I CLKx2 CLKx1 5 Pixel and Control Data QCLK 6 Pixel and Control Data QCLK Table 5-6. Power Supply Current Parameters (3 and 5 V operation) ...
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Bt829B/827B VideoStream II Decoders Figure 5-2. Output Enable Timing Diagram OE Pixel, Clock and Control Data Table 5-8. JTAG Timing Parameters Parameter TMS, TDI Setup Time TMS, TDI Hold Time TCK Asserted to TDO Valid TCK Asserted to TDO Driven ...
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Parametric Information 5.3 Package Mechanical Drawings 5.3 Package Mechanical Drawings Figure 5-4. 100-Pin PQFP Package Mechanical Drawing 114 D829BDSA Bt829B/827B VideoStream II Decoders ...
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Bt829B/827B VideoStream II Decoders 5.4 Revision History Table 5-10. Bt829B Datasheet Revision History Revision Date A 03/27/98 5.0 Parametric Information Description Engineering Release D829BDSA 5.4 Revision History 115 ...
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