em78p257 ELAN Microelectronics Corp, em78p257 Datasheet
em78p257
Available stocks
Related parts for em78p257
em78p257 Summary of contents
Page 1
... EM78P257 8-BIT MICRO-CONTROLLER Version 1.4 EM78P257 OTP ROM ...
Page 2
... To add AC, DC curve 1.4 To remove prescalers from TCCA, TCCB and TCCC Application Note AN-001 EM78P257 Firmware programming for Mouse, Comparator, IR and Change Interrupt. Internal C, External R Oscillation Mode Application Note AN-002 EM78P257 applied by Comparator, IR ourput and Mouse separately This specification is subject to change without prior notice. ...
Page 3
... GENERAL DESCRIPTION EM78P257A 8-bit microprocessors with low-power, high speed CMOS technology. It features a 2K*13 bits Electrical One Time Programmable Read Only Memory (OTP -ROM) and provides a protect bit to prevent from intruding on code, as well as 12 Option bits to accommodate user’s requirements. This specification is subject to change without prior notice. ...
Page 4
... Five interrupt sources * TCC overflow interrupt * Input-port status changed interrupt(wake up from the sleep mode) * External interrupt * IR OUT interrupt * Comparators status change interrupt • Programmable free running watchdog timer • 8 programmable pull-high I/O pins This specification is subject to change without prior notice. 4 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 5
... Two clocks per instruction cycle. • Package types pin DIP 300mil * 20 pin DIP 300mil * 18 pin SOP 300mil * 20 pin SOP 300mil * 20 pin SSOP 209mil • Power on voltage detector available for both EM78P257A and EM78P257B. This specification is subject to change without prior notice. : EM78P257AP : EM78P257BP : EM78P257AM : EM78P257BM : EM78P257AKM ...
Page 6
... P54/CIN2-/TCC P71//RESET P60//INT P61/CIN3-/TCC1 P62/CIN3+ P63/CO3 P52/CO2 P53/CIN2+ P54/CIN2-/TCC P71//RESET P60//INT P61/CIN3-/TCC1 P62/CIN3+ P63/CO3 Fig. 1 Pin Assignment - EM78P257AP/AM/AKM This specification is subject to change without prior notice Vss ...
Page 7
... Table 1 Pin Description- EM78P257AP/AM Symbol Pin No. Type VDD 14 OSCI 16 OSCO 15 I/O P70~P71 4,15 I/O P60~P67 6~13 I/O P50~P55 1~3 I/O 16~18 IR OUT 13 O /INT 6 CIN1-,CIN1+ 16,17 CIN2-,CIN2+ 3,2 CIN3-,CIN3+ 7,8 CIN4-,CIN4+ 12,11 CO1,CO2 18,1 O CO3,CO4 9,10 O TCC 3 TCC1,TCC2, ,7,12 TCC3,TCC4 18,17 /RESET 4 VSS 5 Table 2 Pin Description- EM78P257AKM Symbol Pin No. Type VDD 15,16 - OSCI 18 I OSCO ...
Page 8
... Vss Fig. 2 Pin Assignment - EM78P257BP/BM Power supply. * XTAL type: Crystal input terminal or external clock input pin type: RC oscillator input pin. input pin. 8 EM78P257 OTP ROM P57/TCC6 P51/CO1/TCC3 P50/CIN1+/TCC4 P55/CIN1-/OSCI P70/OSCO VDD P67/IR OUT ...
Page 9
... Vin comparator. * Pin CO1~4 are the outputs of the comparators. External Counter input set as /RESET and remains at logic low, the device will be reset. * Voltage on /RESET/Vpp must not exceed Vdd during the normal mode. * Pull_high defined as /RESET. Ground. 9 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 10
... TCC WDT timer Prescaler Interrupt Instruction Register controller R1(TCC) Instruction R4 decoder DATA & CONTROL BUS Comparator COUNTER IOC5 R5 Fig. 3 Functional block diagram 10 EM78P257 OTP ROM R2 STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 ALU R3 ACC P60/INT P61/CIN3-/TCC1 P62/CIN3+ IOC6/7 P63/CO3 ...
Page 11
... cleared. Thus, the computed jump is limited to the first 256 locations of a page. • In case of EM78P257A/B, the second most significant bit(A10) will be loaded with the content of bit PS0 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which write to R2. • ...
Page 12
... A0 Software Interrupt Vector On-chip Program Hardware Interrupt Vector Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8 Fig. 4 Program counter organization 12 EM78P257 OTP ROM 000H Reset Vector 001H Memory 3ECH ~ 3FEH 7FFH 07.27.2004 (V1.4) ...
Page 13
... Register) IOCD0 (Pull-high Control Register) IOCE0 (WDT Control Register) IOCF0 (Interrupt Mask Register) Bank1 Fig. 5 Data memory configuration PS0 EM78P257 OTP ROM IOCX1 PAGE registers Reserve Reserve Reserve Reserve Reserve IOC51 (TCCA Counter) IOC61 (TCCBL Counter) IOC71 (TCCBH Counter) ...
Page 14
... Bits 5~0 are used to select a register (address: 00~0F, 10~3F) in the indirect addressing mode. • See the configuration of the data memory in Fig (Port 5 ~ Port 6) • R5 and R6 are I/O registers. • Only the lower 6 bits of R5 are available.(applicable to EM78P257A) • The upper 2 bits of R5 are fixed to 0. (if EM78P257A is selected (Port • ...
Page 15
... TCCCIF interrupt 1: enable TCCCIF interrupt • Bit 1 Set to “0” as all time. • Bit 0 Not used. This specification is subject to change without prior notice EM78P257 OTP ROM TCCCIF TCCBIF TCCAIF TCCAIE - - TCCCIE - - 07.27.2004 (V1.4) ...
Page 16
... MF1 MF0 IRE Ratio 1:2(default) 1 1:3 1 Fosco Fosc/1 - Fosc/4 Fosc/8 16 EM78P257 OTP ROM Bit2 Bit1 Bit0 TCC Rate - - 1:128 1:256 ...
Page 17
... RF can be cleared by instruction but cannot be set. • IOCF0 is the relative interrupt mask register. 15. R10 ~ R3F • All of these are the 8-bit general purpose registers. This specification is subject to change without prior notice CMP2IF CMP1IF - 17 EM78P257 OTP ROM EXIF ICIF TCIF 07.27.2004 (V1.4) ...
Page 18
... I/O pin into high impedance, while "0" defines the relative I/O pin as output. • Only the higher 2 bits of IOC5 can be defined. (for EM78P257B only) • Only the lower 2 bits of IOC7 can be defined, the others bits are not available. ...
Page 19
... I/O pin Define P50 as a bi-directional I/O pin. • Bit 5 (TCC6E): Control bit used to enable the second input of counter (for EM78P257B only) For EM78P257B MOUSEN equal to ‘1’, pin 20 is defined as another input pin of TCCC. If MOUSEN equal to ‘0’, pin bi-directional I/O pin ...
Page 20
... Pin 13 can choose P66 or TCC2 only. If MOUSEN is ‘1’ and TCC2E of IOC80 is ‘1’ also, then set pin to TCC2, otherwise set to P66 Comparator is CO4 on. For EM78P257A Pin 10 can choose P64 or CO4 only, and decided by COIE4 of IOC90. Pin 11 can choose CIN4+ only. ...
Page 21
... TCCATS of RA. When TCCATS is ‘1’, then Pin 7 is defined as TCC1, otherwise the status is defined as P61. For EM78P257B Pin 10 can choose P63 or CO3 only, and decided by COIE3 of IOC90. Pin 9 can choose CIN3+ only. ...
Page 22
... Bit 5 of Control Register (CONT-5). When TS is ‘1’, then Pin 4 is defined as TCC, otherwise status defined as P54.• Bit 0 (CE1): Comparator (CO1) enable bit 0 = Comparator CO1 is off (default value). For EM78P257A This specification is subject to change without prior notice. 22 EM78P257 OTP ROM 07 ...
Page 23
... Bit 9,8,7 of CODE option. When choice is ‘1,1,1’, then Pin 16 is defined as P55, otherwise the status is defined as OSCI. For EM78P257B Pin 19 can choose P51 or CO1 only, and the choice is decided by COIE1of IOC90. Pin 18 can choose CIN1+ only. ...
Page 24
... CIN4+ CIN4 - 7. IOCB0 (Pull-down Control Register /PD57 /PD56 • Bit 7 (/PD57) Control bit is used to enable the pull-down of P57 pin. (for EM78P257B only) 0: Enable internal pull-down 1: Disable internal pull-down This specification is subject to change without prior notice. N/A 1,2,3, and 4 -> negative inputs, 1,2 CIN2- -> negative input; CIN1- -> normal I/O pin; ...
Page 25
... Bit 7 (/PH57) Use to enable the pull-high of P57 pin. (for EM78P257B only) 0: Enable internal pull-high 1: Disable internal pull-high • Bit 6 (/PH56) Use to enable the pull-high of P56 pin. (for EM78P257B only) • Bit 5 (/PH55) Use to enable the pull-high of P55 pin. • Bit 4 (/PH54) Use to enable the pull-high of P54 pin. ...
Page 26
... CMP3IF interrupt • Bit 5 (CMP2IE) CMP2IF interrupt enable bit. This specification is subject to change without prior notice PSW0 WDT Rate 0 1:1 1 1:2 0 1:4 1 1:8 0 1:16 1 1:32 0 1:64 1 1:128 CMP2IE CMP1IE PPC/CMP 26 EM78P257 OTP ROM PSW2 PSW1 PSW0 EXIE ICIE TCIE 07.27.2004 (V1.4) ...
Page 27
... When TCCBE(IOC80) is “0” THEN TCCBH is disable, TCCBE is”1” then bit length counter. When IR-Mode Down Counter, else Counter. This specification is subject to change without prior notice. 27 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 28
... The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, a WDT time-out (if This specification is subject to change without prior notice. 28 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 29
... This specification is subject to change without prior notice. 2 (one oscillator start-up timer period). 8-Bit Counter (RC MUX Prescaler PSR2~0 (CONT) Prescaler PSW2~0 (IOCE0) Fig. 6 Block Diagram of TCC and WDT 29 EM78P257 OTP ROM Data Bus SYNC TCC (R1) 2 cycles TCC overflow interrupt 07.27.2004 (V1.4) ...
Page 30
... PDRD EM78P257 OTP ROM IOD 07.27.2004 (V1.4) ...
Page 31
... Fig. 10 Block Diagram of I/O Port 5 with Input Change Interrupt/Wake-up This specification is subject to change without prior notice. PCRD PCWR _ CLK CLK PDWR PDRD CLK EM78P257 OTP ROM IOD TI n 07.27.2004 (V1.4) ...
Page 32
... VDD=3V, Setup time period = 1.22ms ± 30%. This specification is subject to change without prior notice. (II) Port 5 Input Status Change Interrupt 1. Read I/O Port 5 (MOV R5,R5) 2. Execute "ENI" 3. Enable interrupt (Set IOCF0. Port 5 change (interrupt) Interrupt vector (3FEH 1ms (one oscillator start-up timer 32 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 33
... Port 5 input status changed (if enabled). (4) Comparator status changed. The first two cases will cause the EM78P257A/B to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Case 3 is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up ...
Page 34
... In a similar way, if the Comparator Status Changed Interrupt is used to wake-up the EM78P257A/B , the following instructions must be executed before SLEP: MOV A, @0bxx000110 CONTW CLR R1 MOV A, @0bxxxx1110 CONTW WDTC MOV A, @0b0xxxxxxx IOW RE MOV A, @0b1111xxxx IOW RF ENI (or DISI) SLEP NOP One problem user must be aware of, is that after waking up from the sleep mode, WDT will enable automatically. ...
Page 35
... TCCC7 TCCC6 TCCC5 TCCC4 TCCC3 TCCC2 TCCC1 TCCC0 LTR7 LTR6 LTR5 LTR4 EM78P257 OTP ROM Bit 3 Bit 2 Bit 1 Bit /PD53 /PD52 /PD51 /PD50 OD63 ...
Page 36
... P P P57 P56 P55 P54 P67 P66 P65 P64 EM78P257 OTP ROM Bit 3 Bit 2 Bit 1 Bit HTR3 HTR2 HTR1 HTR0 PTR3 ...
Page 37
... CMP4IF CMP3IF CMP2IF CMP1IF EM78P257 OTP ROM Bit 3 Bit 2 Bit 1 Bit P71 P70 ...
Page 38
... This specification is subject to change without prior notice. Bit 7 Bit 6 Bit previous value before reset. VDD D Q CLK CLR WDT Timeout Setup time Fig. 11 Block Diagram of Reset of Controller 38 EM78P257 OTP ROM Bit 4 Bit 3 Bit 2 Bit CLK Reset 07.27.2004 (V1.4) Bit 0 P ...
Page 39
... WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode *P: Previous value before reset This specification is subject to change without prior notice. RST Event RST EM78P257 OTP ROM ...
Page 40
... Port 5 pin will have this feature if its status changes The Port 5 Input Status Change Interrupt will wake up the EM78P257A/B from the sleep mode enabled prior to going into the sleep mode by executing SLEP instruction. When wake-up occurs, the controller will continue to execute program in-line if the global interrupt is disabled ...
Page 41
... /IRQn CLK /RESET Interrupt sources ENI/DISI In EM78P257A/B, each individual interrupt source has its own interrupt vector as depicted in Table 9. Table 9 Interrupt vector Interrupt vector 3EC 3EE 3F0 3F2 3F4 3F6 3F8 3FA 3FC 3FE This specification is subject to change without prior notice. ...
Page 42
... TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0 TCCC6 TCCC5 TCCC4 LTR6 LTR5 LTR4 HTR6 HTR5 HTR4 PTR6 PTR5 PTR4 42 EM78P257 OTP ROM Set predict value TCCCEN Set TCCCIF TCCC Overflow Osci input or External input Bit 3 Bit 2 Bit 1 Bit 0 0 TCCAIE/0 TCCATS/0 TCCATE/0 ...
Page 43
... Comparator EM78P257A/B has four comparators, consisting of two analog inputs and one output. The comparators can be employed to wake up from sleep mode. Fig. 15 and Fig. 16 show the circuit of the comparator ...
Page 44
... CIN4- -> negative input; CIN(1,2,3)- -> normal I/O pin; 3,2 CIN2- -> negative input; CIN3- -> normal I/O pin; 4,2 CIN2- -> negative input; CIN4- -> normal I/O pin; 4,3,2 CIN2- -> negative input; CIN(3,4)- -> normal I/O pin; 1,4,3 CIN3- -> negative input; CIN(1,4)- -> normal I/O pin; 44 EM78P257 OTP ROM Bit 2 Bit 1 Bit 0 CI2 CI1 CI0 Comment 07.27.2004 (V1.4) ...
Page 45
... Fig. 17 shows the comparator output block diagram CMPOUT COIEX Fig. 17 The Output Configuration of a Comparator 3. Programming the Related Registers This specification is subject to change without prior notice COIEX CEX RESET CMPXIE 45 EM78P257 OTP ROM CO1 CO2 CO3 CO4 From OP I/O To CMPXIF 07.27.2004 (V1.4) ...
Page 46
... Oscillator 1. Oscillator Modes The EM78P257A/B can be operated in the five different oscillator modes, such as Internal RC oscillator mode (IRC), RC oscillator with Internal capacitor mode(IC),External RC oscillator mode(ERC), High XTAL oscillator mode(HXT), and Low XTAL oscillator mode(LXT). User can select one of them by programming OSC2,OCS1 and OSC0 in the CODE Option register ...
Page 47
... Two clocks 2. Crystal Oscillator/Ceramic Resonators(XTAL) EM78P257A/B can be driven by an external clock signal through the OSCI pin as shown in Fig.18 below. In most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 19 depicts such circuit. The same thing applies whether the HXT mode or in the LXT mode. ...
Page 48
... This specification is subject to change without prior notice. Frequency Mode Frequency 455 kHz HXT 2.0 MHz 4.0 MHz 32.768kHz LXT 100KHz 200KHz 455KHz 1.0MHz HXT 2.0MHz 4.0MHz Vcc Rext OSCI Cext EM78P257A/B Fig. 20 Circuit for External RC Oscillator Mode 48 EM78P257 OTP ROM C1(pF) C2(pF) 100~150 100~150 20~40 20~40 10~30 10~ 20~40 20~150 15~30 15~ ...
Page 49
... The frequency drift about ±30 Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration, EM78P257A/B also offers a special oscillation mode, which is equipped with an internal capacitor and an external resistor connected to Vcc. The internal capacitor functions as temperature compensator. In order to obtain more accurate frequency, a precise resistor is recommended ...
Page 50
... EM78P257A/B POR voltage range is 1.2V~1.8V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power can be switched ON again. This way, the EM78P257A/B will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed ( less) ...
Page 51
... Fig. 23 Circuit 1 for the residue voltage protection This specification is subject to change without prior notice Fig. 22 External Power on Reset Circuit EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 52
... Fig. 24 Circuit 2 for the residue voltage protection This specification is subject to change without prior notice EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 53
... MOUSE APPLICATION MODE 1. Overview & Features Overview: Fig.25 shows how EM78P257A/B communicates with PS/2 connector of PC. Features: • RC oscillation. • Six photo-couples input. MOUSEN VCC X1(TCC1) 4.5R R 15K MOUSEN VCC X2(TCC2) 4.5R R 15K MOUSEN VCC Y1(TCC3) 4.5R R 15K MOUSEN VCC Y2(TCC4) 4.5R R 15K This specification is subject to change without prior notice. ...
Page 54
... Bit 6 Bit 5 Bit 4 Bit 3 INT/0 TS/0 TE/0 TCC4E/0 TCC6E/0 TCCBE TCCBIE/0 TCCBTS/0 TCCBTE Bit 6 Bit 5 Bit 4 54 EM78P257 OTP ROM After MCU process send data to PC Bit 2 Bit1 Bit 0 0 PSR2/0 PSR1/0 PSR0 TCCAIE/0 TCCATS/0 TCCATE/0 0 TCCCIE/0 TCCCTS/0 TCCCTE/0 ...
Page 55
... This specification is subject to change without prior notice. TCC6 TCC5 TCC4 TCCA6 TCCA5 TCCA4 TCCB6 TCCB5 TCCB4 TCCBTS TCCBTE - 55 EM78P257 OTP ROM TCC3 TCC2 TCC1 TCC0 0 TCCCIF TCCBIF TCCAIF TCCA3 TCCA2 TCCA1 TCCA0 TCCB3 TCCB2 TCCB1 TCCB0 TCCAIE TCCATS ...
Page 56
... MOUSE mode Timing (1)Photo-couples pulse width: X1(Y1) X2(Y2) Counter increment if the rising/falling edge leading the one on X2. Counter decrement if the rising/falling edge falling behind the one on X2. (2) Sending DATA (data from EM78P257A/B to system) This specification is subject to change without prior notice ...
Page 57
... CLK to an inactive level prior to the tenth clock. If EM78P257A/B transmission is beyond the tenth clock, the system receives the data. If EM78P257A/B is not transmitting or if the system choose to override the output, the system forces CLK to an inactive level for a period of not less than 100us while preparing for output ...
Page 58
... DATA to low, and clock once more. If framing error occurs, EM78P257A/B continues to clock until DATA is high, then clocks the line control bit and requests for a Resend. When the system sends out a command or data transmission that requires a response, the system waits for EM78P257A/B to respond before sending its next output ...
Page 59
... Overview & Features Overview: EM78P257A/B is designed for use in universal infrared remote commander applications. Fig.26 shows the hardware modulator of EM78P257A/B. It can generate programmable pulse trains for driving an infrared LED. Features: • Power saving : Idle and Stop modes are provided • Hardware Modulator providing pulse bursts , with : ...
Page 60
... Fig. 27 Hardware Modulator =(decimal value held in High-time register)/fosco 60 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 61
... This specification is subject to change without prior notice. = 20mA, when the output voltage drops to 2.4V, at Vdd = 5V IROUT ;(Enable IR) ;(Enable TCCBH) ;(Select control register segment 1) ;(Set Low-Time Register=10h) ;(Set High-Time Register=20h) ;(Set pulse number = 5 => LSB=5, MSB=0) ;LSB=5 ;MSB=0 61 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 62
... MF0/0 Bit 6 Bit 5 Bit 4 TCCBL6 TCCBL5 TCCBL4 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0 LTR6 LTR5 LTR4 HTR6 HTR5 HTR4 PTR6 PTR5 PTR4 62 EM78P257 OTP ROM Bit 3 Bit 2 Bit1 Bit 0 0 TCCCIE/0 TCCCTS/0 TCCCTE IRE/0 HF/0 LGP/0 PWM/0 Bit 3 Bit 2 Bit1 Bit 0 ...
Page 63
... Disable IRE. Disable H/W Modulator Function. This specification is subject to change without prior notice TCCBTS TCCBTE - TCC6E TCCBE - MF1 MF0 IRE Ratio 1:2(default) 1:3 1:4 - Fosco Fosc/1 - Fosc/4 Fosc/8 63 EM78P257 OTP ROM TCCCIE TCCCTS TCCCTE LGP PWM 07.27.2004 (V1.4) ...
Page 64
... Fig. 28 CASE 1shows a typical pulse train(DP=00;MF=10;HF=0;LGP=0;PWM=0); CASE 2 shows the sa me pulse train after being modulated with a frequency of 1/4Fosc (DP=00 ;MF=10 ;HF=1;LGP=0;PWM=0). This specification is subject to change without prior notice. High-time Register = 2 Interrupt to CPU Number of pulses = 2 64 EM78P257 OTP ROM start Software time 07.27.2004 (V1.4) ...
Page 65
... Fig. 30 Continuous pulse train (DP=00;MF=10;HF=0;LGP=0;PWM==1). 4.13 CODE OPTION EM78P257A/B has one CODE option word and one Customer ID word, which are not a part of the normal program memory. Word 0 Bit12~Bit0 Code option12~0 1 ...
Page 66
... Bit 6 (/PTB): Protect bit. 0: Enable 1: Disable • Bit 5 (SUT): Set-Up Time of device bits. SUT 1 0 *Theoretical values, for reference only • Bit 4 (TYP): Type selection for EM78P257A or EM78P257B. TYPE 0 1 • Bit 3 (RCOUT): A selecting bit of Oscillator Output or I/O port for RC Oscillator. RCOUT 0 1 • ...
Page 67
... Table 33 The List of the Instruction Set of EM78P257A/B INSTRUCTION BINARY HEX ...
Page 68
... R(n+1), RLC R R( R(0-3) A(4-7), SWAPA R R(4-7) A(0-3) SWAP R R(0-3) R(4-7) JZA R R+1 A, skip if zero JZ R R+1 R, skip if zero BC R,b 0 R(b) BS R,b 1 R(b) JBC R,b if R(b)=0, skip JBS R,b if R(b)=1, skip PC+1 [SP], CALL k (Page EM78P257 OTP ROM C None T,P T,P None <Note1> None None None PC None None None <Note1> Z,C,DC None Z Z Z,C,DC Z,C, Z,C,DC Z,C, ...
Page 69
... This instruction cannot operate under RF. This specification is subject to change without prior notice. JMP k (Page MOV A A AND A,k A & XOR A RETL k [Top of Stack] SUB A,k k-A A INT PC+1 [SP], 001H ADD A,k k EM78P257 OTP ROM None None None PC Z,C,DC None PC Z,C,DC 07.27.2004 (V1.4) ...
Page 70
... " 0 " This specification is subject to change without prior notice. 2.0 2 0.8 0 EM78P257 OTP ROM 07.27.2004 (V1.4) ...
Page 71
... ABSOLUTE MAXIMUM RATINGS Items Temperature under bias Storage temperature Input voltage Output voltage This specification is subject to change without prior notice. Rating -65 C -0.3V to -0. EM78P257 OTP ROM 70 C 150 C +6.0V +6.0V 07.27.2004 (V1.4) ...
Page 72
... Fosc=32KHz (Crystal type, two clocks), output pin floating, WDT enabled /RESET= 'High', Fosc=2MHz (Crystal type, two clocks), output pin floating /RESET= 'High', Fosc=4MHz (Crystal type, two clocks), output pin floating 72 EM78P257 OTP ROM Min Typ Max Unit DC 4 MHz DC ...
Page 73
... The duration of watch dog timer is determined by option code (bit5). This specification is subject to change without prior notice. Conditions Min 45 Crystal type 100 RC type 500 (Tins+20)/N* 10. 2000 10. 0. Cload=20pF 73 EM78P257 OTP ROM Typ Max Unit 15.4 20 15.4 20 ...
Page 74
... Fig. 31 Vth (Threshold voltage) of Port5, Port6 and Port7 vs. VDD This specification is subject to change without prior notice. Vih/Vil (Input pins with inverter) typ 25¢J min (-0¢J to 70¢J) 3.3 3.8 4.3 Vdd(Volt) 74 EM78P257 OTP ROM 4.8 5.3 07.27.2004 (V1.4) ...
Page 75
... Fig. 32 Port5, Port6 and Port7 Voh vs. Ioh, VDD=5V This specification is subject to change without prior notice Min 70 ¢J -4 Typ 25 ¢J -6 Max 0 ¢ 0 Fig. 33 Port5, Port6 and Port7 Voh vs. Ioh, VDD=3V 75 EM78P257 OTP ROM Voh /Ioh (VDD=3V) 1.5 2 2.5 3 Voh(Volt) 07.27.2004 (V1.4) ...
Page 76
... Fig. 34 Port5, Port6 and Port7 Vol vs. Iol, VDD=5V This specification is subject to change without prior notice Fig. 35 Port5, Port6 and Port7 Vol vs. Iol VDD=3V 76 EM78P257 OTP ROM Max 0 ¢J Typ 25 ¢J Min 70 ¢J 0.5 1 1.5 2 2.5 3 Vol(Volt) 07.27.2004 (V1.4) ...
Page 77
... Max 70 ¢J 20 Typ 25 ¢J Min 0 ¢ 2.3 2.8 3.3 3.8 4.3 VDD (Volt) Fig. 36 WDT time out period vs. VDD This specification is subject to change without prior notice. 4.8 5.3 77 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 78
... Fig. 38 Typical RC OSC Frequency vs. Temperature (R and C are ideal components) This specification is subject to change without prior notice 3. 5. 10K R = 100K 0 2.5 3 3.5 4 4.5 5 VDD(Volt) 78 EM78P257 OTP ROM 5.5 06.27.2003(V1.2) ...
Page 79
... Fig. 40 Internal RC 32K and 455KHz OSC Frequency vs. Temperature Join Process Drifts, VDD=3V This specification is subject to change without prior notice. OSC = 4MHz OSC = 1MHz Temperature (¢J) OSC = 455KHz OSC = 32KHz Temperature (¢J) 79 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 80
... Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows : ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable This specification is subject to change without prior notice. OSC = 4MHz OSC = 1MHz Temperature (¢J) OSC = 455KHz OSC = 32KHz Temperature (¢J) 80 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 81
... Fig. 44 Maximum operating current (ICC1 and ICC2) vs. Temperature This specification is subject to change without prior notice. Typ. ICC2 Typ. ICC1 Temperature(¢J) Maximum ICC1 and ICC2 VS. Temperature Max. ICC2 Max. ICC1 Temperature(¢J) 81 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 82
... ISB1: VDD=5V, WDT disable ISB2: VDD=5V, WDT enable This specification is subject to change without prior notice. Typical ICC3 and ICC4 VS. Temperature Typ. ICC4 Typ. ICC3 Temperature (¢J) Max. ICC4 Max. ICC3 Temperature (¢J) 82 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 83
... Fig. 48 Maximum standby current (ISB1 and ISB2) vs. Temperature This specification is subject to change without prior notice. Typ. ISB2 Typ. ISB1 Temperature (¢J) ISB1 and ISB2 VS. Temperature Max. ISB2 Max. ISB1 Temperature (¢J) 83 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 84
... 2.5 2 Max. 1.5 1 0.5 0 2.3 2.8 3.3 3.8 4.3 V(Volt) Fig. 50 V-I curve in operating mode, operating frequency is 4MHz This specification is subject to change without prior notice Min 2.3 2.8 4.8 5.3 Fig. 51 V-I curve in operating mode, operating 84 EM78P257 OTP ROM OSC = 32KHz Max. Min. 3.3 3.8 4.3 4.8 5.3 Voltage(V) frequency is 32K Hz 06.27.2003(V1.2) ...
Page 85
... APPENDIX Package Types OTP MCU Package Type EM78P257AP EM78P257AM EM78P257AKM EM78P257BP EM78P257BM This specification is subject to change without prior notice. Pin Count DIP 18 SOP 18 SSOP 20 DIP 20 SOP 20 85 EM78P257 OTP ROM Package Size 300mil 300mil 209mil 300mil 300mil 06.27.2003(V1.2) ...
Page 86
... Package Information 18-Lead Plastic Dual in line (PDIP) ¡X 300 mil This specification is subject to change without prior notice. 86 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 87
... Plastic Small Outline (SOP) ¡X 300 mil This specification is subject to change without prior notice. 87 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 88
... Lead Plastic Shrink Small Outline (SSOP) ¡X 209 mil This specification is subject to change without prior notice. 88 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 89
... Plastic Dual in line (PDIP) ¡X 300 mil This specification is subject to change without prior notice. 89 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 90
... Plastic Small Outline (SOP) ¡X 300 mil This specification is subject to change without prior notice. 90 EM78P257 OTP ROM 06.27.2003(V1.2) ...
Page 91
... Products in this website is only for your reference. The actual specifications and applied technology will be based on each confirmed order. ELAN reserves the right to modify the information without prior notification. The most up-to-day information is available on the website http://www.emc.com.tw. This specification is subject to change without prior notice. 91 EM78P257 OTP ROM 06.27.2003(V1.2) ...