em78p257 ELAN Microelectronics Corp, em78p257 Datasheet - Page 29
em78p257
Manufacturer Part Number
em78p257
Description
8-bit Microcontroller
Manufacturer
ELAN Microelectronics Corp
Datasheet
1.EM78P257.pdf
(91 pages)
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4.4 I/O Ports
This specification is subject to change without prior notice.
TE (CONT)
(IOCE0)
TCC Pin
WDTE
WDT
The I/O registers, (Port 5, Port 6, and Port 7), are bi-directional tri-state I/O ports. Port 5 is pulled-high internally by
software. Likewise, P6 has its open-drain output also through software. Port 5 features an input status changed
interrupt (or wake-up) function and is pulled-down by software. Each I/O pin can be defined as "input" or "output" pin
by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable.
The I/O interface circuits for Port 5, Port 6 and Port7 are shown in Fig. 7, Fig. 8, and Fig. 9 respectively.
enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode
by software programming. Refer to WDTE bit of IOCE0 register. With no prescaler, the WDT time-out period is
approximately 18 ms
1
2
NOTE:
NOTE:
CLK (Fosc/2 or Fosc/4)
VDD=5V, Setup time period = 15.4ms ± 30%.
VDD=3V, Setup time period = 17.6ms ± 30%.
VDD=5V, Setup time period = 1.07ms ± 30%.
VDD=3V, Setup time period = 1.22ms ± 30%.
WDT Time out
8-Bit counter
8 to 1 MUX
1
0
1
or 1ms
TS (CONT)
MUX
2
(one oscillator start-up timer period).
Fig. 6 Block Diagram of TCC and WDT
8-Bit Counter (RC)
29
8 to 1 MUX
Prescaler
Prescaler
PSR2~0
(CONT)
PSW2~0
(IOCE0)
2 cycles
SYNC
EM78P257
TCC overflow
07.27.2004 (V1.4)
OTP ROM
TCC (R1)
Data Bus
interrupt
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