l29c520 LOGIC Devices Incorporated, l29c520 Datasheet

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l29c520

Manufacturer Part Number
l29c520
Description
4 X 8-bit Multilevel Pipeline Register
Manufacturer
LOGIC Devices Incorporated
Datasheet

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DEVICES INCORPORATED
FEATURES
L29C520/521 B
DEVICES INCORPORATED
Four 8-bit Registers
Implements Double 2-Stage Pipeline
or Single 4-Stage Pipeline Register
Hold, Shift, and Load Instructions
Separate Data In and Data Out Pins
High-Speed, Low Power CMOS
Technology
Three-State Outputs
Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
Package Styles Available:
• 24-pin PDIP
• 28-pin PLCC, J-Lead
CLK
D
I
8-0
1-0
8
2
LOCK
D
IAGRAM
The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
The Instruction pins, I
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I
may be set to prevent any register
from changing.
DESCRIPTION
REG 1
REG 2
REG 3
REG 4
4 x 8-bit Multilevel Pipeline Register
1
1-0
, control the
4 x 8-bit Multilevel Pipeline Register
8
2
Y
OE
S
7-0
1-0
1-0
The S
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
S
I
H
H
I
H
H
H
H
T
L29C520 I
L
L
T
L29C521 I
L
L
T
L
L
1
1
1
ABLE
ABLE
ABLE
L29C520/521
S
I
H
H
I
H
H
H
H
L
L
L
L
L
L
0
0
1-0
0
Description
D R1 R1 R2 R2 R3 R3 R4
HOLD
D R1 R1 R2 HOLD
ALL REGISTERS ON HOLD
Description
D R1 R1 R2 R2 R3 R3 R4
HOLD
D R1 HOLD
ALL REGISTERS ON HOLD
Register Selected
Register 4
Register 3
Register 2
Register 1
select lines control a 4-to-1
1.
2.
3. O
Pipeline Registers
NSTRUCTION
NSTRUCTION
HOLD
HOLD
UTPUT
L29C520/521
S
D R3
D R3
HOLD
08/02/2000–LDS.520/1-P
ELECT
T
T
ABLE
ABLE
R3 R4
HOLD
HOLD
HOLD

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l29c520 Summary of contents

Page 1

... R1 and shifted sequentially through R2, R3, and R4. Also, for the L29C520, data may be loaded from the inputs into either with only shifting. The L29C521 differs from the L29C520 in ...

Page 2

... Test Condition V = Min –15 Min 24 (Note 3) Ground V V (Note 12 Ground V V (Note 12) OUT CC (Notes 5, 6) (Note 7) 2 L29C520/521 Voltage Supply Min Typ Max Unit 2.4 V 0 0.0 0 µA 20 µ ...

Page 3

... L29C520/521– Max Min Max ...

Page 4

... Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 4 L29C520/521 11. For the t test, the transition is ENA measured to the 1.5 V crossing point with datasheet loads. For the t the transition is measured to the ± ...

Page 5

... DEVICES INCORPORATED L29C520 — ORDERING INFORMATION 24-pin — 0.3" wide CLK GND 12 Plastic DIP (P2) Speed 0°C to +70°C — C OMMERCIAL 22 ns L29C520PC22 –55°C to +125°C — C OMMERCIAL – ...

Page 6

... DEVICES INCORPORATED L29C520 — ORDERING INFORMATION ...

Page 7

... S CREENING S CREENING OMPLIANT 7 L29C520/521 ...

Page 8

... C OMMERCIAL –55°C to +125°C — MIL-STD-883 8-bit Multilevel Pipeline Register CREENING S CREENING OMPLIANT 8 L29C520/521 Pipeline Registers 08/02/2000–LDS.520/1-P ...

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