l29c525 LOGIC Devices Incorporated, l29c525 Datasheet

l29c525

Manufacturer Part Number

l29c525

Description

Dual Pipeline Register

Manufacturer

LOGIC Devices Incorporated

Datasheet

1.L29C525.pdf (6 pages)

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DEVICES INCORPORATED

FEATURES

L29C525 B

DEVICES INCORPORATED

Dual 8-Deep Pipeline Register

Configurable to Single 16-Deep

Low Power CMOS Technology

Replaces AMD Am29525

Load, Shift, and Hold Instructions

Separate Data In and Data Out Pins

Three-State Outputs

Package Styles Available:

• 28-pin Plastic DIP

• 28-pin Plastic LCC, J-Lead

CLK

7-0

1-0

LOCK

IAGRAM

The L29C525 is a high-speed, low

power CMOS pipeline register. It is

pin-for-pin compatible with the AMD

Am29525. The L29C525 can be

configured as two independent 8-level

pipelines or as a single 16-level

pipeline. The configuration imple-

mented is determined by the instruc-

tion code (I

The I

internal routing of data and loading of

each register. For instruction I

(Push A and B), data applied at the

on the rising edge of CLK. The

contents of A0 simultaneously move

to register A1, A1 moves to A2, and so

on. The contents of register A7 are

wrapped back to register B0. The

registers on the B side are similarly

shifted, with the contents of register

B7 lost.

DESCRIPTION

7-0

inputs is latched into register A0

1-0

instruction code controls the

1-0

) as shown in Table 2.

1-0

= 00

Dual Pipeline Register

Instruction I

similarly to the Push A and B

instruction, except that only the B side

registers are shifted. The input data is

applied to register B0, and the

contents of register B7 are lost. The

contents of the A side registers are

unaffected. Instruction I

A) is identical to the Push B

instruction, except that the A side

registers are shifted and the B side

registers are unaffected.

Instruction I

internal data movement. It is equiva-

lent to preventing the application of a

clock edge to any internal register.

The contents of any of the registers is

selectable at the output through the

use of the S

independence of the I and S control

lines allows simultaneous reading and

writing. Encoding for the S

is given in Table 3.

Dual Pipeline Register

Pipeline Registers

3-0

1-0

L29C525

control inputs. The

= 01 (Push B) acts

= 11 (Hold) causes no

03/23/2000–LDS.29C525-G

1-0

L29C525

= 10 (Push

3-0

controls

7-0

3-0

Related parts for l29c525

l29c525 Summary of contents

Page 1

... I 1-0 2 CLK Dual Pipeline Register DESCRIPTION The L29C525 is a high-speed, low power CMOS pipeline register pin-for-pin compatible with the AMD Am29525. The L29C525 can be configured as two independent 8-level pipelines single 16-level pipeline. The configuration imple- mented is determined by the instruc- tion code ( shown in Table 2 ...

Page 2

... Pipeline Registers 03/27/2000–LDS.29C525-G L29C525 HOLD ...

Page 3

... Test Condition V = Min – Min (Note 3) Ground V V (Note 12 Ground V V (Note 12) OUT CC (Notes 5, 6) (Note 7) 3 L29C525 Dual Pipeline Register Voltage Supply Min Typ Max Unit 2.4 V 0 0.0 0 µ ...

Page 4

... L29C525– ...

Page 5

... CC ENA OE 1 Measured V with I = –10mA and Measured V with I = –10mA and Pipeline Registers 03/32/2000–LDS.29C525-G L29C525 test, DIS C IRCUIT EVELS t DIS 3.5V Vth 0 0 Vth = 10mA OL = 10mA OL ...

Page 6

... Top GND View D GND Plastic J-Lead Chip Carrier (J4) S OMMERCIAL CREENING L29C525JC20 L29C525JC15 S OMMERCIAL CREENING OMPLIANT Pipeline Registers 03/27/2000–LDS.29C525-G ...

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