cxd2548r Sony Electronics, cxd2548r Datasheet
cxd2548r
Available stocks
Related parts for cxd2548r
cxd2548r Summary of contents
Page 1
... CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD2548R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter on a single chip ...
Page 2
... Interface A/D CONVERTER OpAmp – 2 – CXD2548R AOUT1 98 98 AIN1 99 99 LOUT1 100 100 AOUT2 109 109 AIN2 108 108 LOUT2 107 107 33 XRST 15 15 XROF 27 27 LOCK 77 ...
Page 3
... AV 2 111 112 – 3 – CXD2548R ASYO ASYI 52 BIAS 51 50 RFAC 49 AV ...
Page 4
... MNT1 output. 30 MNT1 MNT3 output. 31 MNT3 Vss1 Digital GND. 33 DOUT Digital Out output pin. Anti-shock pin. 34 ATSK I Mirror signal output. 35 MIRR Defect signal output. 36 DFCT Description 1, 1/2 or 1/4, or low output is selected and output. – 4 – CXD2548R ...
Page 5
... Digital GND. 68 TEST I Test pin. Normally fixed to low. 69 SFDR Sled drive output. 70 SRDR Sled drive output. 71 TFDR Tracking drive output. 72 TRDR Tracking drive output. 73 FFDR Focus drive output. Description , high = – 5 – CXD2548R = AV = 5.0V) DD ...
Page 6
... Master clock 16.9344MHz crystal oscillation circuit output. 105 XVss Master clock analog GND. 106 AVss2 R ch, analog GND. 107 LOUT2 O Analog R ch, LINE output. 108 AIN2 I R ch, operational amplifier input. 109 AOUT2 O Analog R ch, analog output. Description – 6 – CXD2548R ...
Page 7
... The GFS signal goes high when the frame sync and the insertion timing match. • RFCK is derived from the crystal accuracy, and has a cycle of 136µs (during normal speed). • C2PO represents the data error status. • XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. Description – 7 – CXD2548R ...
Page 8
... I = 0.36mA ( 5.5V – ( 1.5 to 3.5V – ( 5.0V – 5.5V – – 8 – CXD2548R Max. Unit Applicable pins 0.4 ...
Page 9
... Input amplitude V 2 5.0V ± 5 Typ. Max. Unit MHz 5.0V ± 5 Typ. Max. Unit 500 ns ns 500 1,000 0 WLX WHX 5.0V ± 5 Typ. Max. Unit V + 0.3 Vp-p DD – 9 – CXD2548R V IHX V 0.9 IHX 0.1 IHX V ILX ...
Page 10
... WCK 1 5.0V ± 5 Min. Typ (BCKI) t (BCKI (PCMDI) (PCMDI (LRCKI) – 10 – CXD2548R 0V, Topr = –20 to +75°C) SS Max. Unit ...
Page 11
... When settings related to DFCT signal generation are Typ. t SPW ··· 1/f SCLK ··· MSB Unit Min. Typ. Max. 1 MHz 500 ns 15 µ 0V, Topr = –20 to +75° Min. Typ. Max. Unit 40 kHz 40 kHz 5 kHz B – 11 – CXD2548R LSB Conditions ...
Page 12
... Analog characteristics ( Conditions Crystal 384Fs 768Fs 384Fs 768Fs 680p 12k 22µ 100k LPF external circuit diagram 768Fs/384Fs Rch RF CXD2548R Lch – 12 – CXD2548R = 5.0V 0V 25° Min. Typ. Max. Unit 0.0050 0.0070 % 0.0045 0.0065 96 100 dB 96 100 SHIBASOKU (AM51A) ...
Page 13
... DD Item Symbol Output voltage V OUT Load resistance R L When a sine wave of 1kHz and 0dB is output. Applicable pins 1 LOUT1, LOUT2 = AV = 5.0V 0V, Topr = –20 to +75° Min. Typ. Max. 1.15 8 – 13 – CXD2548R Unit Applicable pins Vrms ...
Page 14
... List of Servo Filter Coefficients ...................................................................................................... 102 §4-20. FILTER Composition ..................................................................................................................... 104 §4-21. TRACKING and FOCUS Frequency Response ............................................................................ 111 [5] Application Circuit §5-1. Application Circuit .......................................................................................................................... 112 Explanation of abbreviations AVRG: Average AGCNTL: auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 14 – CXD2548R ...
Page 15
... The interface timing chart is shown below. 750ns or more CLOK DATA (Example) XLAT Registers • The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low. D18 D19 D20 D21 D22 D23 – 15 – CXD2548R 750ns or more Valid ...
Page 16
... CXD2548R ...
Page 17
... CXD2548R ...
Page 18
... CXD2548R ...
Page 19
... CXD2548R ...
Page 20
... CXD2548R ...
Page 21
... CXD2548R ...
Page 22
... CXD2548R ...
Page 23
... CXD2548R ...
Page 24
... CXD2548R ...
Page 25
... CXD2548R ...
Page 26
... CXD2548R ...
Page 27
... CXD2548R ...
Page 28
... FOCUS GAIN DOWN LOW BOOST FILTER B-L K2A 82 FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED CONTENTS – 28 – CXD2548R ...
Page 29
... FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 29 – CXD2548R ...
Page 30
... TRK In Reg. FCS In Reg. TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC In Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS OV64 0 – 30 – CXD2548R Output data length — — — — — — 8 bit 8 bit 8 bit 8 bit 9 bit 9 bit 9 bit 9 bit ...
Page 31
... RXF = 0 FORWARD RXF = 1 REVERSE D22 D21 D20 0.09ms 0.02ms 0.05ms 0.18ms 0.09ms 0.05ms D20 D22 D21 5.8ms 2.9ms 1.45ms Data 1 Data – 31 – CXD2548R Data 3 Data ...
Page 32
... CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing Processing Application 1 Anti-rolling is enhanced. Sync window protection is enhanced. – 32 – CXD2548R Data 3 D15 D14 D13 D12 KSL3 KSL2 KSL1 KSL0 See "$BX Commands". ...
Page 33
... Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. – 33 – CXD2548R 1 , and the output is 1 and the output is 1 and the output is 1 and the output is 1/8 ...
Page 34
... CXD2548R ...
Page 35
... Zero detection mute off. Data 3 and subsequent data are DF/DAC function settings. Data 2 Data 3 D20 D19 to D16 D15 D14 D13 MCSL CKOSL1 CKOSL0 ZDPL ZMUT Processing Processing Processing Processing Processing – 35 – CXD2548R Data 4 D12 D11 D10 D9 D8 — — ...
Page 36
... Data 2 and subsequent data are DF/DAC function settings. Data 2 D20 D19 D18 D17 D16 ATT 0 0 OPSL EMPH SMUT Data AD4 AD3 AD2 AD1 AD0 Processing Processing Processing Processing Processing – 36 – CXD2548R Data 3 D15 D14 D13 D12 0 AD9 AD8 Data FMUT ...
Page 37
... The attenuation data is 10 bits, and is set as follows. Attenuation data Audio output 3FFh 3FEh –0.0085dB 3FEh –0.017dB : 001h –60.198dB 000h Command bit FMUT = 1 Forced mute on. FMUT = 0 Forced mute off. FMUT can be set when OPSL is high. Processing 0dB – Processing – 37 – CXD2548R ...
Page 38
... CXD2548R ...
Page 39
... C1F1 C1F2 C1 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Command bit CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. Description C2F1 C2F2 C2 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Processing – 39 – CXD2548R ...
Page 40
... The maximum value during peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak detection register. Peak detection can also be performed for previous value hold and average value interpolation data – 40 – CXD2548R ...
Page 41
... CLVP mode gain setting: GMDP, GMDS Gain Gain GMDP MDP1 MDP0 0 0 –6dB 0 1 0dB 1 0 +6dB D21 D20 D22 Gain Gain Gain MDP0 MDS0 MDS1 Gain CLVS Gain Gain MDS1 MDS0 – 41 – CXD2548R GMDS –6dB 0dB +6dB ...
Page 42
... The rotational velocity R of the spindle can be expressed with the following equation. 256 – Relative velocity at normal speed = 1 n: VP0 to 7 setting value F0 VP0 to 7 setting value [HEX] Fig. 2-1. – 42 – CXD2548R Data 3 D15 D14 D13 D12 VP3 VP2 VP1 VP0 32 ...
Page 43
... CLV CLV CAV CAV-W – 43 – CXD2548R Data 3 D16 D15 D14 D13 D12 SFSL VC2C HIFC LPWR VPON Description 1 Description Crystal reference CLV servo. Used for playback in CLV-W 2 mode. Spindle control with VP0 to 7. Spindle control with the external ...
Page 44
... Gain Gain CAV1 CAV0 0 0 0dB 0 1 –6dB 1 0 –12dB 1 1 –18dB Command bit FCSW = 0 The VPCO2 pin is not used and it is Hi-Z. FCSW = 1 The VPCO2 pin is used and the pin signal is the same as VPCO1 CAV-W mode. Processing – 44 – CXD2548R ...
Page 45
... Timing chart KICK 2-2 (a) 0 BRAKE 2-2 (b) STOP 2-2 (c) KICK 2-3 (a) 0 BRAKE 2-3 (b) STOP 2-3 (c) KICK 2-4 (a) BRAKE 2-4 (b) 0 STOP 2-4 (c) KICK 2-5 (a) 1 BRAKE 2-5 (b) STOP 2-5 (c) KICK 2-6 (a) BRAKE 2-6 (b) 0 STOP 2-6 (c) KICK 2-7 (a) BRAKE 2-7 (b) 1 STOP 2-7 (c) LPWR Timing chart 0 2-8 0 2-9 0 2-10 1 2-11 0 2-12 (EPWM = 0) 1 2-13 (EPWM = 0) 0 2-14 (EPWM = 1) 1 2-15 (EPWM = 1) – 45 – CXD2548R ...
Page 46
... MDS Z Z MDP L H MON (b) BRAKE BRAKE MDS L H MDP L H MON (b) BRAKE BRAKE MDS Z Z MDP L H MON (b) BRAKE – 46 – CXD2548R STOP Z MDS MDP Z MON L (c) STOP STOP MDS MDP L MON L (c) STOP STOP MDS Z MDP Z MON L (c) STOP ...
Page 47
... MON (a) KICK BRAKE MDS Z Z MDP H MON (b) BRAKE BRAKE MDS Z MDP L H MON (b) BRAKE BRAKE Z MDS Z MDP H MON (b) BRAKE – 47 – CXD2548R STOP MDS Z Z MDP MON L (c) STOP STOP MDS Z MDP Z H MON (c) STOP STOP Z MDS MDP Z H MON (c) STOP ...
Page 48
... MDS Acceleration MDP 264kHz 3.8µs Timing Chart 2-11 CLV-W mode DCLV PWM LPWR = 1 MDS Acceleration MDP 264kHz 3.8µ · 236 (ns Acceleration n · 236 (ns The BRAKE pulse is masked when LPWR = 1. – 48 – CXD2548R Z Deceleration Deceleration Z Deceleration Z ...
Page 49
... Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM CLV-W and CAV-W modes. The BRAKE pulse is masked when LPWR = 1. Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 49 – CXD2548R Z Deceleration Z Deceleration ...
Page 50
... In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. • See Timing Chart 2-17. • The high and low intervals for SQCK should be between 750ns and 120µs. – 50 – CXD2548R ...
Page 51
... Timing Chart 2-16 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO S0· Same 400ns max S0 · S0·S1 Same Sub Code P.Q.R.S.T.U.V.W Read Timing – 51 – CXD2548R ...
Page 52
... CXD2548R ...
Page 53
... CXD2548R ...
Page 54
... VF0 the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load m – 54 – CXD2548R ...
Page 55
... Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding the servo output block). Note) The capture range for this mode is theoretically up to the signal processing limit. – 55 – CXD2548R ...
Page 56
... Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E800 Mute OFF $A000 CAV-W $E665 (CLVA) NO ALOCK = H ? YES CLV-W $E60C (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 56 – CXD2548R Operation mode Spindle mode Time ...
Page 57
... For C2 correction, the code is created with 24-byte information and 4-byte C2 parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD2548R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. • The correction status can be monitored externally. ...
Page 58
... Dependent on error condition MNT3 C1 correction MNT1 MNT0 3-4. DA Interface • The CXD2548R's DA interface is as follows. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. C2 correction Strobe – 58 – CXD2548R ...
Page 59
... CXD2548R ...
Page 60
... Servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the servo, but can be sent to the CXD2548R. Connect the CPU and RF as shown in Fig. 3-3. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µ ...
Page 61
... In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. CXD2548R connection diagram when using auto sequence (example) RF FOK ...
Page 62
... COUT is used for counting the number of jumps. The N-track move is 16 executed only by moving the sled, and is therefore suited for moving across several thousand to several ten- thousand tracks. Blind E Fig. 3-4-(b). Auto Focus Timing Chart – 62 – CXD2548R $08 tracks, note that the 16 ...
Page 63
... SSP $28 ($2C) Fig. 3-5-(b). 1-Track Jump Timing Chart Track (REV kick for Track kick REV jump) sled servo WAIT (Blind A) COUT = NO YES (FWD kick for Track REV REV jump) kick WAIT (Brake B) Track sled servo ON END Brake B $2C ($28) $25 – 63 – CXD2548R ...
Page 64
... Fig. 3-6-(b). 10-Track Jump Timing Chart 10 Track Track, sled FWD kick WAIT (Counts COUT 5) (Blind A) COUT = YES Track, REV kick C = Over-flow ? NO (Check whether the COUT cycle is longer than overflow C.) YES Track sled servo ON END COUT 5 count $2E ($2B) – 64 – CXD2548R Over-flow C $25 ...
Page 65
... Fig. 3-7-(b). 2N-Track Jump Timing Chart 2N Track Track, sled FWD kick WAIT (Blind A) Counts COUT till N < 16. COUT (MIRR Counts MIRR till N NO YES Track REV kick C = Over-flow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Over-flow C $2E ($2B) $26 ($27) – 65 – CXD2548R 16. Kick D $25 ...
Page 66
... SSP Fig. 3-8-(b). N-Track Move Timing Chart N Track move Track servo OFF Sled FWD kick WAIT (Blind A) Counts COUT till N < 16. COUT (MIRR Counts MIRR till N NO YES Track, sled servo OFF END END COUT (MIRR) N count – 66 – CXD2548R 16. $20 ...
Page 67
... Asymmetry Compensation Fig. 3-9 shows the block diagram and circuit example BIAS Fig. 3-9. Asymmetry Compensation Application Circuit ASYO R1 R2 ASYI – 67 – CXD2548R ...
Page 68
... EFM signal pulses. The block diagram of this PLL is shown in Fig. 3-10. The CXD2548R has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. ...
Page 69
... X'tal XTSL 2/1 MUX Digital PLL Spindle rotation information 1/2 1/32 1/2 1/n Microcomputer 256 control (VP7 to 0) VCOSEL2 1/K VCO2 (KSL1, 0) VPON 1/M 1/N 1/K VCO1 (KSL3, 2) VCOSEL1 RFPLL CXD2548R – 69 – CXD2548R CLV-W CAV-W VPCO1, 2 CLV-N CLV-W /CLV-N LPF CAV-W VCTL V16M VCKI PCO FILI FILO CLTV ...
Page 70
... MDP error: Phase error for CLVP servo PWMI: MDS Error Measure 2/1 MUX Gain MDS Over Sampling Filter-2 Noise Shape Modulation PWMI Mode Select MDS MDP Spindle drive signal from the microcomputer Fig. 3-11. Block Diagram – 70 – CXD2548R MDP Error Measure Over Sampling Filter-1 Gain MDP 1/2 MUX CLV P/S ...
Page 71
... DAC block input timing Timing Chart 3-3 shows the DAC block input timing chart. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD2548R. This is to allow data to be sent to the DAC block via the audio DSP, etc. ...
Page 72
... CXD2548R ...
Page 73
... LPF Block The CXD2548R contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency determined flexibly. The reference voltage ( ( The LPF block application circuit is shown below. ...
Page 74
... Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks (in CLV-N mode) (a) CD-DSP block In the CXD2548R, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X. CD-DSP block playback speed X'tal XTSL ...
Page 75
... Output format: 7-bit PWM Others: Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz Input range: 2.15V to 5.0V Others: RF zero level automatic measurement The signal input from the RFDC pin is multiplied by a factor of 0.7 and loaded into the A/D converter. – 75 – CXD2548R ...
Page 76
... AVRG (Average) Measurement and Compensation The CXD2548R has a circuit that measures AVRG of RFDC, VC, FE, and TE and a circuit that compensates them to control servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2548R, and is able to cancel the offset by performing each AVRG measurement before playback operation and using these results for compensation ...
Page 77
... The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register. • FLC1 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register. • FLC0 The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register. – 77 – CXD2548R ...
Page 78
... The number of steps by which the count value changes can be selected from steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to approximately 3.9 [mV]. A: Register mode B: Counter mode C:Counter mode (when stopped) – 78 – CXD2548R ...
Page 79
... CXD2548R ...
Page 80
... The default settings aim for 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. Max. 11.4µs Timing Chart 4-2. – 80 – CXD2548R AGCNTL completion ...
Page 81
... The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2548R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0 ...
Page 82
... FOCUS SERVO OFF, 0V OUT 0 1 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE Table 4-2. $02 $03 and performing only FCS search. $00 $02 $03 FCSDRV RF FOK FE 0 FZC – 82 – CXD2548R : Don't care $08 Fig. 4-5. ...
Page 83
... D17 and D16 when D19 = D18 = 0 is set SLED KICK LEVEL (basic value SLED KICK LEVEL (basic value SLED KICK LEVEL (basic value SLED KICK LEVEL (basic value Table 4-4. – 83 – CXD2548R : Don't care ±1) ±2) ±3) ±4) ...
Page 84
... Fig. 4-7.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 –Peak Hold1 DFCT MIRR Comp (Mirror comparator level Fig. 4-6. SDF (Defect comparator level Fig. 4-7. – 84 – CXD2548R ...
Page 85
... When the serial data is $1, vibration detection can be monitored from the SENS pin. Anti Shock TE Filter TRK Gain Up Filter TRK Gain Normal Filter Hold Filter DFCT Servo Filter Fig. 4-8. ATSK Comparator TRK PWM Gen Fig. 4-9. – 85 – CXD2548R Hold register EN SENS ...
Page 86
... ANTI SHOCK ON 0 ANTI SHOCK OFF 1 BRAKE ON BRAKE OFF 0 TRACKING GAIN NORMAL 0 1 TRACKING GAIN UP 1 TRACKING GAIN UP FILTER SELECT 1 0 TRACKING GAIN UP FILTER SELECT 2 Fig. 4-5. – 86 – CXD2548R Outer track Inner track REV FWD Servo ON JMP JMP Fig. 4-11. : Don't care ...
Page 87
... SCLK t SCLK pulse width SPW t Delay time DLS Table 4-6. During readout, the upper 8 bits of the serial data must be 39 (Hex). t SPW ··· 1/f SCLK MSB ··· Fig. 4-12. Typ. Max. Unit Min. 1 MHz ns 500 µs 15 – 87 – CXD2548R LSB ...
Page 88
... TFDR MCK 2 2 FRDR/ TRDR 180ns MCK 5.6448MHz Output value –A 64t MCK At MCK 32t 32t 32t MCK MCK t MCK MCK MCK 2 2 Timing Chart 4-3. – 88 – CXD2548R Output value 0 64t MCK 32t 32t MCK MCK MCK ...
Page 89
... Example of Drive Circuit 22k RDR FDR 22k Fig. 4-13. Operational Amplifier Drive Circuit 22k 22k – 89 – CXD2548R V CC DRV V EE ...
Page 90
... Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. Both types of conversion are calculated at V change proportionally. (Voltage conversion = V = 5.0V. If this voltage changes, the conversion values also DD / used supply voltage) DDX DDX – 90 – CXD2548R ...
Page 91
... FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D10 FB9 FB8 FB7 FB6 FB5 D10 TV9 TV8 TV7 TV6 TV5 – 91 – CXD2548R — FB4 FB3 FB2 FB1 — ...
Page 92
... FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FTZ Focus search speed 0 6.73V/s 0 3.36 0 2.24 0 1.68 1 8.97 1 5.38 1 4.49 1 3.85 D10 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 – 92 – CXD2548R ...
Page 93
... Default value: 0 (low) AGHS: AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGHT: AGCNTL high sensitivity adjustment time (128/256ms) Default value: 0 (256ms) D10 Slice level +500mV +250 +125 +62.5 FE/TE input conversion 63mV 125 125mV 250 – 93 – CXD2548R ...
Page 94
... Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. All commands are on when set to 1. D10 – 94 – CXD2548R ...
Page 95
... FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal – 95 – CXD2548R Readout data length 8 bit 16 bit 8 bit 8 bit 9 bit 9 bit 8 bit 8 bit 9 bit 9 bit 9 bit ...
Page 96
... Number of steps sampling cycle of the focus servo filter. 1 When MCK is 128Fs, the sampling 2 frequency is 88.2kHz. When converted input, 1 step is approximately 3.9 [mV]. 8 Relative gain TPS1 0dB 0 +6dB 0 +12dB 1 +18dB 1 – 96 – CXD2548R TPS0 Relative gain 0 0dB 1 +6dB 0 +12dB +18dB 1 ...
Page 97
... Default value: 011 (313mV) RFDC input conversion SFOX SFO2 D10 SFO1 Slice level 0 0 179mV 0 1 223 1 0 268 1 1 313 0 0 357 0 1 446 1 0 536 1 1 625 – 97 – CXD2548R ...
Page 98
... This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. Slice level 89mV 134 179 224 DFCT maximum time No timer limit 2.00ms 2.36 2.72 Count-down speed [V/ms] [kHz] 0.246 22.05 0.492 44.1 0.984 88.2 1.969 176.4 Count-down speed [V/ms] [kHz] 1.969 176.4 3.938 352.8 7.875 705.6 15.75 1411.2 – 98 – CXD2548R ...
Page 99
... When the MIRR signal can be input from an external source through the MIRR pin. XT1D: The clock input from FSTI can be used as the master clock for the servo block regardless of the XTSL pin, XT2D and XT4D by setting D10 – 99 – CXD2548R MIRI XT1D ...
Page 100
... TE/FE input conversion 0 31 [mV [mV] 0 125 [mV] 1 250 [mV] Frequency division ratio According to XTSL (default) 1/2 1/4 – 100 – CXD2548R LPAS SRO1 SRO0 AGHF COT2 These settings are the same as for both focus auto gain control and tracking auto gain control. ...
Page 101
... Serial data input D/A Analog output Clock input Latch enable input Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. – 101 – CXD2548R ··· ··· MSB ··· LSB LSB To the 7-segment LED To the 7-segment LED MSB To an oscilloscope, etc ...
Page 102
... FOCUS GAIN DOWN LOW BOOST FILTER B-L K2A 82 FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED CONTENTS – 102 – CXD2548R ...
Page 103
... K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 103 – CXD2548R ...
Page 104
... FCS K2B Hold Reg 1 M05 –1 Z K28 K2A 2 –7 2 –7 K29 Note) Set the MSB bit of the K27 and K29 coefficients to 0. – 104 – CXD2548R FCS AUTO Gain M06 M07 K13 K11 –1 Z K10 2 7 FCS PWM FCS SRCH FCS ...
Page 105
... Z K1E K20 2 –7 2 –7 K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. M0E K3E –1 Z K3D – 105 – CXD2548R TRK AUTO Gain M0E M0F K22 K23 –1 Z K21 7 2 TRK PWM TRK JMP TRK AUTO Gain ...
Page 106
... K03 2 –7 2 –7 K04 Note) Set the MSB bit of the K02 and K04 coefficients to 0. Slice M09 –1 –1 Z K14 K15 – 106 – CXD2548R TRK AUTO Gain M0E M0F K3E K23 –1 Z K3D 7 2 TRK PWM TRK JMP TRK AUTO Gain ...
Page 107
... Z Z K49 K4B –7 – K4A K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 107 – CXD2548R M0A Anti Shock K35 Comp Reg –1 Z K33 K34 AVRG Reg TRK K45 Hold Reg FCS ...
Page 108
... K0D K0E FCS K2B Hold Reg 1 M05 –1 Z K28 80H –7 –7 – K29 K2A – 108 – CXD2548R FCS AUTO Gain M06 M07 K11 K13 Z –1 K10 7 2 FCS PWM FCS SRCH FCS AUTO Gain M06 M07 K2D K13 – ...
Page 109
... M0D –1 Z K1E 80H –7 –7 – K1F K20 M0E K3E –1 Z K3D –7 2 – 109 – CXD2548R TRK AUTO Gain M0E M0F K22 K23 –1 Z K21 7 2 TRK PWM TRK JMP TRK AUTO Gain 2 7 M0F K23 TRK PWM ...
Page 110
... Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and the K36, K37 and K3C coefficients during quasi double accuracy to 0. M0D Z –1 K3A 80H –7 –7 – K3B K3C – 110 – CXD2548R TRK AUTO Gain M0E M0F K3E K23 Z –1 K3D 7 2 TRK PWM TRK JMP ...
Page 111
... NORMAL GAIN UP 10 100 1K f – Frequency [Hz] FOCUS frequency response NORMAL GAIN DOWN 10 100 1K f – Frequency [Hz] – 111 – CXD2548R 180° 90° G 0° –90° –180° 20K 180° 90° G 0° –90° –180° 20K ...
Page 112
... – 112 – CXD2548R DD DD ...
Page 113
... EIAJ CODE JEDEC CODE 112PIN LQFP(PLASTIC) 22.0 ± 0.2 20.0 ± 0 0.65 0.32 ± 0.05 M 0.13 S 0.32 ± 0.05 (0.3) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-112P-L01 LQFP112-P-2020 LEAD MATERIAL PACKAGE WEIGHT – 113 – CXD2548R 1.7MAX 1.4 ± 0 EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g ...