m65818afp Renesas Electronics Corporation., m65818afp Datasheet
m65818afp
Related parts for m65818afp
m65818afp Summary of contents
Page 1
... Digital Amplifier Processor of S-Master* Technology Description The M65818AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing. The M65818AFP has built-in 24bit sampling rate converter and digital-gain-controller. ...
Page 2
... External Input 24bit LRCK BCK CD DVD Audio DATA 32kHz etc. to 192kHz 256fsi Clock /512fsi DSD Interface SACD Rev.1.00, Sep.04.2003, page M65818AFP Level Sampling ∆Σ Control Rate Converter +30dB to DSD Clock MCU I/F 1024fs/512fs Stream LC Power Filter Driver PWM Stream ...
Page 3
... M65818AFP 1. Pin Configuration (Top View) (3.3V/5V System INIT 41 SYNC 42 DATA 43 BCK 44 LRCK 45 FsiI 46 DSD128Fs 47 DSD64Fs 48 DSDR 49 DSDL 50 DSDCKSEL1 51 DSDCKSEL2 52 DSDCKIO 53 TEST1 54 TEST2 55 CKCTL1 56 CKCTL2 57 BFVdd 58 EXIOSEL 59 EXDATAL 60 EXDATAR 61 EXBCK 62 EXWCK 63 ...
Page 4
... M65818AFP A-1 Difference between M65818AFP and M65817AFP M65818AFP has added the following functions to M65817AFP. M65817AFP PWM Output Form General Pulse Width Modulation Reverse Output Reverse Phase between Pins Function of PWM OUTL1+/R1+ and OUTL1-/R1- Output "OUTL1-/R1-" ∆Σ Operation Ratio 16fso Fixed ...
Page 5
... M65818AFP 2. Block Diagram Rev.1.00, Sep.04.2003, page ...
Page 6
... M65818AFP 3. Pin Descriptions Pin No. Name I/O Description 1 OUTR2+ O Rch PWM2(+) Output 2 VddR2+ Power Supply for Rch PWM2(+) (5V) 3 VddR2- Power Supply for Rch PWM2(-) (5V) 4 OUTR2- O Rch PWM2 (-) Output 5 VssR2- GND for Rch PWM2(-) 6 VssR1- GND for Rch PWM1(-) 7 OUTR1- O Rch PWM1 (-) Output ...
Page 7
... M65818AFP Pin No. Name I/O Description 41 INIT I Initialize Input(Power Supply Reset): ; L:Reset, H:Release 42 SYNC I Synchronous Set of System Clock (at Rising Edge) 43 DATA I DATA Input (CD/MD / DVD audio mode) PCM Signal 44 BCK I BCK Input (CD/MD / DVD audio mode) PCM Signal 45 LRCK I LRCK Input (CD/MD / DVD audio mode) PCM Signal ...
Page 8
... M65818AFP Pin No. Name I/O Description 77 XfsoOUT O Buffered Output of Secondary Master Clock (1024/512fso) 78 XOVss GND for Secondary Master Clock Buffer 79 VssR GND for Rch PWM 80 VssR2+ GND for Rch PWM2(+) 4. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Supply Voltage PWMVdd BFVdd DVdd Input Voltage Range Vi (5 ...
Page 9
... M65818AFP DC Characteristics Parameter Symbol H Level Input Voltage VIH5 VIH3 L Level Input Voltage VIL5 VIL3 Input Leak Current Ileak "H"Level Output DSD128Fs VOH5 Voltage DSD64Fs VOH3 EXDATAL EXDATAR EXBCK EXWCK CKOUT1 VOH5 CKOUT2 VOH3 CKOUT3 XfsoOUT VOH5 OFLFAG VOH3 SFLAG FsoCKO ...
Page 10
... M65818AFP • Normal mode The Normal is data input mode from CD,MD,DVD etc. Input pins are DATA,BCK, and LRCK. • External 8fs Data mode In this mode, the 8fs rate data inputted from external device. Input pins are EXDATAL,EXDATAR,EXBCK and EXWCK. The data synchronized with the clock of EXBCK,EXWCK pins are inputted into EXDATAL,EXDATAR pins . ...
Page 11
... M65818AFP 5.2. SCDT, SCSHIFT, SCLATCH SCDT,SCSHIFT,and SCLATCH are input pins for setting M65818AFP's operation. Input format of SCDT, SCSHIFT and SCLATCH is shown below. • Input format of SCDT, SCSHIFT, and SCLATCH. 24 SCDT SCSHIFT SCLATCH • Mode Setting The operating Mode are classified in four and assigned by bit1and bit2. These four functions are shown below. ...
Page 12
... M65818AFP • Input Formats of DATA, BCK, and LRCK LRCK BCK MSB DATA (24bit) LRCK BCK DATA (16bit) DATA (20bit) MSB DATA (24bit) LRCK BCK LSB DATA (24bit) LRCK BCK 1 BCK MSB DATA (24bit) 5.4. EXBCK, EXWCK, EXDATAL, EXDATAR, EXIOSEL When "input signal mode" is "external 8fs data mode", regardless of a setup of EXIOSEL pin, the data of 8fs rate are inputted from EXDATAL, EXDATAR pins. By setup of serial control " ...
Page 13
... M65818AFP In case an external 8fs data input is primary side synchronous , the data is inputted to Sampling Rate Converter Block. When "input signal mode" is except a "external 8fs data mode", the output data of sampling rate converter are outputted from EXDATAL,EXDATAR pins setting up EXIOSEL pin into "H". ...
Page 14
... M65818AFP Setting of DSDCKIO is following table. DSDCKIO L H • SACD Input Format mode1 DSDL/R (input data) DSD128fs DSD64fs mode2 DSDL/R (input data) DSD128fs DSD64fs mode3 DSDL/R (input data) DSD128fs DSD64fs mode4 DSDL/R (input data) DSD128fs DSD64fs * D0:Positive phase data, Positive phase data are fetched at the timing of "O" marks in upper figure. ...
Page 15
... H 5.9. FsoCKO FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency is free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65818AFP,take a synchronization between M65818AFP and other external devices. Detail explanation is shown in next paragraph, "SYNC". 5.10. SYNC, FsoI, FsiI, SFLAG M65818AFP synchronizes in clock input from the external source devices ...
Page 16
... The primary side: It synchronizes with LRCK. All ICs synchronize with an input device by connecting common LRCK. The Secondary side: It synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. ...
Page 17
... Master IC.FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. Moreover, the rise edge of FsoCKO sent from M65818AFP and the rise edge of EXWCK (8fs) which comes from the external device need to be with a synchronous phase. ...
Page 18
... Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as ` forced-disable`. The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. ...
Page 19
... M65818AFP The examples of a connection diagram The case of the multi use (6ch) in each input mode are shown in the following figure. Normal Mode LRCK (Primary) External 8fs Data Mode (The Case of Primary Side Synchronization) ASYNCEN1=don't care ASYNCEN2=enable Master LRCK FsiI EXWCK (Primary) ...
Page 20
... M65818AFP The examples of a connection diagram The case of the single use (2ch) in each input mode are shown in the following figure. Normal Mode ASYNCEN1=don't care ASYNCEN2=enable LRCK (Primary) LRCK FsiI EXWCK External 8fs Data Mode (The Case of Primary Side Synchronization) ASYNCEN1=don't care ...
Page 21
... M65818AFP 5.11. OFLFLAG OFLFLAG pin is output the 'over flow flag' in the operation. OFLFLAG pin outputs "H" level by detection of over flow from Gain Control Block and others. The "H" level width is over 0.6msec, so detection result is held. 5.12. OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, OUTR2- OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, and OUTR2- pins are pulse output modulated ∆ ...
Page 22
... Resynchronization treatment, which is same at SYNC function. 5.16. TEST1, TEST2, TEST3 TEST1,TEST2, and TEST3 pins are test input for factory shipping test of M65818AFP. TEST1,TEST2, and TEST3 pins must be tied to "L" level on usual operation. 5.17. Power Supply and GND Power supply and GND routes have 5 isolated lines ...
Page 23
... M65818AFP (5)BFVdd, BFVss These pins are Power supply and GND for input/output buffer (3.3V/ case that BFVdd pin is applied at 5.0V, input/output voltage level of 34-67pins becomes 5.0V signal level. In another case that BFVdd pin is supplied at 3.3V, input/output pins (34-67 pins) becomes 3.3V signal level. 5.18. Power sequences System power-on sequencing * Refer to following figure ...
Page 24
... Gain Data Mantissa (LSB) • Output Limit (bit5,bit6:NSLMT1 ,NSLMT2 ) The M65818AFP has Over Flow Limit function which detects by input signal level and limit gain control. Limit value is set by Gain Control Mode :bit5,bit6 ”NSLMT1, NSLMT2” and System2 Mode:bit17"NSOBIT". The limit value setting of Gain control block and PWM output. ...
Page 25
... M65818AFP Table (6-1-1b). Limit Value [In the case of 5bit mode System2 mode:bit17(NSOBIT)="H"] DSLMT1 DSLMT2 Limit Value of Gain L L ±0.90625 H L ±0.875 L H ±0.84375 H H ±0.8125 • Channel Selection for Gain Control Block (bit7,bit8:GCONT1 ,GCONT2 ) These bit selection enable to control gain data "L/R common" or "L/R independence". ...
Page 26
... M65818AFP Table (6-1-2). The Gain Data and Output Level Gain Data Polarity 10100/11111111 (b) to 10001/10000000 (b) to 10000/10000000 (b) 01111/11111111 (b) to 00000/10000000 (b) to 00000/00000001 (b) 00000/00000000 (b) • Calculation method of Gain value. The way to calculation of Gain value from Gain Data is following equation. <Index data (decimal value)-16> ...
Page 27
... M65818AFP • Operating time of Soft Mute Total steps from Maximum value(10100b/11111111b) to Minimum value(00000b/00000000b) (128steps/1 index) × (20index (10100b-10000b)) +256steps = 2816steps. The transition term of up and down depend on 2fso clock. Therefore, in case of fso=48kHz, T=1/2fso=10.416µsec/step, transition term are following. From Maximum value (10100b/11111111b) to Minimum value (00000b/00000000b) : 2816T=29.333msec. ...
Page 28
... M65818AFP 6.2. System1 Mode bit Flag Name Functional Explanation 1 MODE1 Mode Setting 1 2 MODE2 Mode Setting 2 3 IFMT0 Input Format Selection 4 IFMT1 5 IBIT0 Setting for Input Word Length 6 IBIT1 7 ISF0 Input Sampling Rate Selection 8 ISF1 9 EMPFS1 Fs selection for De-emphasis Filter 10 EMPFS2 11 DF1IMUTE ...
Page 29
... M65818AFP Table 6-2-4 Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L) bit Flag Name 9 EMPFS1 10 EMPFS2 Table 6-2-5 Selection of PWM Output form bit Flag Name 22 PWMMODE0 23 PWMMODE1 *Output Form 2 is available only under following conditions. MCKSEL="L" (Secondary Side Master Clock 1024fso) , Serial Control System2 mode, ...
Page 30
... Under condition of ASYNCEN1 ="L", primary side asynchronous detection is unavailable whether the clock is not inputted to FsiI pin, thereby M65818AFP does not operate function under asynchronization, for instance mute operation. However, Primary Side Asynchronous Detection is available only condition of `SACD-Fsi` mode. ...
Page 31
... M65818AFP *NOTE2; Selection of PWM output form Pay attention in selection and setting above-mentioned that a noise may occur by internal clock changes when setting of MCKSEL pin is changed and the serial control System2 mode: bit17 (NSOBIT) and bit16 (NSSPEED). Since especially MCKSEL pin sets up an internal master clock, use with a fixed value recommended. ...
Page 32
... ASYNCEN2 : "L"…disable. "H"…enable. Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous position, whether Fsol Clock is not inputted, there by M65818AFP does not operate function for instance mute operation. Rev.1.00, Sep.04.2003, page ROM1 ...
Page 33
... M65818AFP • Reverse Lch/Rch for PWM Output pins(bit9: CHSEL). "L": Lch/Rch no reverse, "H": Lch/Rch reverse. • ∆Σ : Rch Input Phase (bit10: DRPOL). "L"…. Same phase ("Through") "H"…..This setting makes ∆Σ Rch Input in reverse, further makes PWM block input phase reverse, ultimately phase becomes positive phase ( Input pin and Output pin's phase is same). • ...
Page 34
... M65818AFP • ∆Σ Block: AC dithering Rch Phase (bit21: ACDRPOL). "L"…Same phase "H"…Reverse phase • ∆Σ Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2). 7.1. AC Characteristics Lists. AC Characteristics Parameter Symbol XfsoIN duty ratio duty(XfsoIN) XfsiIN duty ratio duty(XfsiIN) SCSHIFT pulse time ...
Page 35
... M65818AFP 7.2. AC Characteristics Timing Chart (1) XfsoIN, XfsiIN Duty Ratio twh (2) SCSHIFT, SCDT, SCLATCH input timing Chart tw(SCSHIFT) SCSHIFT th(SCDT) tsu(SCDT) SCDT SCLATCH (3) BCK, DATA, and LRCK Input timing Chart tw(BCK) BCK DATA LRCK (4) EXBCK, EXDATAL, EXDATAR, EXWCK input timing Chart tw(EXBCK) EXBCK ...
Page 36
... M65818AFP (6) DSD64Fs, DSD128Fs, DSDL, DSDR Input Timing Chart mode1 tw(DSDCK128) DSD128Fs DSD64Fs DSDL DSDR mode2 tw(DSDCK64) DSD64Fs DSDL DSDR mode3 tw(DSDCK128) DSD128FS DSD64Fs DSDL DSDR mode4 DSD64Fs DSDL DSDR Rev.1.00, Sep.04.2003, page tw(DSDCK128) tw(DSDCK64) tsu(DSDCK64) th(DSDCK64) tsu(DATA) th(DATA) tw(DSDCK64) ...
Page 37
... X X MCKSEL XFsoIN (Secondary Side Clock XFsoOUT OUTL1+ OUTL1- OUTL2+ OUTL2- OUTR1+ M65818AFP OUTR1- OUTR2+ OUTR2- FsoCKO FsoI CKCTL1 CKCTL2 O F CKOUT1 CKOUT2 CKOUT3 ...
Page 38
... M65818AFP Package Dimensions Rev.1.00, Sep.04.2003, page ...
Page 39
Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...