hy5du561622ct-d4 Hynix Semiconductor, hy5du561622ct-d4 Datasheet

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hy5du561622ct-d4

Manufacturer Part Number
hy5du561622ct-d4
Description
256m-p Ddr Sdram
Manufacturer
Hynix Semiconductor
Datasheet

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HY5DU561622CT-D4
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HYNIX
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8
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Oct. 2003
HY5DU561622CT-D4/D43
256M-P DDR SDRAM
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43

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hy5du561622ct-d4 Summary of contents

Page 1

... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 ...

Page 2

... JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch • Full and Half strength driver option controlled by EMRS OPERATING FREQUENCY Package Grade Speed 400mil - D4 200MHz 66pin - D43 200MHz TSOP-II HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 PRELIMINARY Remark (CL-tRCD-tRP) DDR400 (3-4-4) DDR400 (3-3-3) 3 ...

Page 3

... VDD 33 34 64Mx4 32Mx8 16M 4banks 4banks A0 - A12 A0 - A12 A0-A9, A11 A0-A9 BA0, BA1 BA0, BA1 A10 A10 8K 8K HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 x16 x8 x4 VSS VSS VSS DQ15 DQ7 NC VSSQ VSSQ VSSQ DQ14 NC NC DQ13 DQ6 DQ3 ...

Page 4

... DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 4 ...

Page 5

... Bank0 Control 16Mx4 / Bank1 16Mx4 / Bank2 16Mx4 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL DQS CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 4 DQS DQ[0:3] DQS Data Strobe Transmitter Data Strobe Receiver 5 ...

Page 6

... Bank0 Control 8Mx8 / Bank1 8Mx8 / Bank2 8Mx8 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL DQS CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 8 DQS DQ[0:7] DQS Data Strobe Transmitter Data Strobe Receiver 6 ...

Page 7

... Bank2 4Mx16 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL LDQS UDQS CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 16 LDQS, UDQS LDM, UDM 32 16 DQ[0:15] LDQS, UDQS Data Strobe Transmitter Data Strobe Receiver 7 ...

Page 8

... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 A10/ WE ADDR BA Note code 1 code 1,5 ...

Page 9

... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.3 / Oct. 2003 CKEn /CS, /RAS, /CAS, / HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 ADD A10 Note ...

Page 10

... X X DSEL NOP BST L H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Action 3 NOP or power down 3 NOP or power down 4 ILLEGAL 4 ILLEGAL 4 ILLEGAL Row Activation NOP 5 Auto Refresh or Self Refresh Mode Register Set NOP NOP 4 ILLEGAL ...

Page 11

... READ/READAP L L BA, CA, AP WRITE/WRITEAP H H BA, RA ACT H L BA, AP PRE/PALL AREF/ SREF L L OPCODE MRS HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Action 4 ILLEGAL Term burst, precharge 11 ILLEGAL 11 ILLEGAL Continue burst to end Continue burst to end ILLEGAL 10 ILLEGAL 10 ILLEGAL 4,10 ILLEGAL 4,10 ILLEGAL 11 ILLEGAL 11 ...

Page 12

... DSEL NOP BST L H BA, CA, AP READ/READAP HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD 4 ILLEGAL 4,10 ILLEGAL 4,10 ILLEGAL 4,9,10 ILLEGAL 4,10 ILLEGAL 11 ILLEGAL 11 ILLEGAL NOP - Enter ROW ACT after tWR ...

Page 13

... L BA, CA, AP WRITE/WRITEAP H H BA, RA ACT H L BA, AP PRE/ PALL AREF/ SREF L L OPCODE MRS HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Action 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD 11 ILLEGAL 11 ILLEGAL 11 ILLEGAL 11 ...

Page 14

... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP , continue self refresh X INVALID X Exit power down, enter idle ...

Page 15

... ACT POWER DOWN PDEN BST PDEX BANK ACTI VE WRITE READ READAP WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITEAP WRITE PRE(PALL) PRE- CHARGE POWER-UP POWER APPLIED HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 SELF REFRESH AUTO REFRESH READ READ Command Input Automatic Sequence 15 ...

Page 16

... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.3 / Oct. 2003 Sequencing Voltage relationship to avoid latch-up After or with VDD HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 16 ...

Page 17

... EMRS Set MRS Set Precharge All Reset DLL Auto Refresh (with A8 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 AREF MRS ACT RD CODE CODE CODE CODE CODE CODE CODE ...

Page 18

... Reserved Reserved Operating Mode 0 Normal Operation HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Burst Length A3 Burst Type 0 Sequential 1 Interleave Burst Length A1 A0 Sequential Interleave 0 0 Reserved Reserved ...

Page 19

... A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Sequential ...

Page 20

... Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are included in this document. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 20 ...

Page 21

... This part do not support /QFC function, A2 must be programmed to Zero. Rev. 0.3 / Oct. 2003 Operating Mode Operating Mode Normal Operation All other states reserved HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DLL A0 DLL enable 0 Enable 1 Diable Output Driver A1 ...

Page 22

... VIN(DC) -0.3 VID(DC) 0.36 VI(RATIO the transmitting device, and to track variations in the dc level of the same. HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Rating Unit -55 ~ 125 o C -0.5 ~ 3.6 V -0.5 ~ 3.6 V -0 260 ˜ ˜sec = 0V) SS Max ...

Page 23

... Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced Test Condition -D4 115 125 Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) Speed Unit Note -D43 120 mA 130 ...

Page 24

... Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced Test Condition -D4 115 125 Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) Speed Unit Note -D43 120 mA 130 ...

Page 25

... Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced Test Condition -D4 120 135 Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) Speed Unit Note -D43 125 mA 140 ...

Page 26

... DDR400(200Mhz, CL=3) : tCK = 5ns, CL=3, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : RA0 A2 RA1 A3 RA2 N RA3 repeat the same timing with random address changing 50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N= NOP Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 26 ...

Page 27

... C, Voltage referenced Symbol Min 0.31 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ o (TA Voltage referenced to VSS = 0V) Value V DDQ V DDQ V REF V REF HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) Max Unit Note 0.31 V REF DDQ 0.5*V +0 DDQ Unit REF 1.5 V ...

Page 28

... Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition Rev. 0.3 / Oct. 2003 Parameter Max. amplit ude=1. Time(ns) Parameter Max. amplitude= 1. Time(ns) HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Specification DDR333 DDR200/266 1.5V 1.5V 1.5V 1. Overshoot V DD Ground Undershoot 6 Specification DDR333 DDR200/266 1 ...

Page 29

... HP tQH -t QHS min tHP (tCL,tCH) tQHS - tHZ tAC(Max) tLZ tAC(min) tAC(Max) tAC(min) tAC(Max) tIS 0.6 tIH 0 0.7 IH HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DDR400 (D43) Unit Min Max - 70K 40 70K ns tRCD tRAS(min ...

Page 30

... Write DQS Postamble Time Mode Register Set Delay Exit self refresh to non-READ command Exit self refresh to READ command Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DDR400 (D4) DDR400 (D43) Symbol Min Max Min t 2 ...

Page 31

... Rev. 0.3 / Oct. 2003 Delta tIS Delta tIH +50 0 +100 0 Delta tDS Delta tDH +75 +75 +150 +150 Delta tDS Delta tDH ps ps +50 +50 Delta tDS Delta tDH +50 +50 +100 +100 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 31 ...

Page 32

... These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 32 ...

Page 33

... CK, /CK, CKE CK, /CK All other input-only pins All other input-only pins DQ, DQS, DM DQ, DQS VDDQ/2, V peak-to-peak = 0. = Zo= REF C =30pF L HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Symbol Min Max Unit C 2.0 3 Delta 2.0 3 Delta C - 0.5 pF ...

Page 34

... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 0.3 / Oct. 2003 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Unit : mm(Inch Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) 34 ...

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