hy5du561622ftp-4 Hynix Semiconductor, hy5du561622ftp-4 Datasheet
hy5du561622ftp-4
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hy5du561622ftp-4 Summary of contents
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... HY5DU561622FTP-5 / HY5DU561622FTP-4 256M(16Mx16) DDR SDRAM HY5DU561622F(L)TP-5 HY5DU561622F(L)TP-4 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Mar. 2008 1 ...
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... Revision History Revision No. 1.0 First Version Release Correction 1.1 - P.3 Ordering Information Rev. 1.1 / Mar. 2008 History 1HY5DU561622FTP-5 HY5DU561622FTP-4 Draft Date Remark Nov. 2007 Mar. 2008 2 ...
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... Part No. (VDD, VDDQ) HY5DU561622FTP-4 2. 0.2V HY5DU561622FTP-5 2. 0.2V Rev. 1.1 / Mar. 2008 1HY5DU561622FTP-5 HY5DU561622FTP-4 • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Write mask byte controls by LDM and UDM • Programmable /CAS latency supported • ...
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... Pin Pitch ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh 1HY5DU561622FTP-5 HY5DU561622FTP DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 ...
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... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. 1HY5DU561622FTP-5 HY5DU561622FTP-4 5 ...
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... W rite Data Register 2-bit Prefetch Unit Bank 4Mx16/Bank0 Control 4Mx16 /Bank1 4Mx16 /Bank2 4Mx16 /Bank3 Mode Row Decoder Column Decoder Column Address Counter CLK, DLL /CLK Block Mode Register 1HY5DU561622FTP-5 HY5DU561622FTP Data Strobe CLK_DLL Transmitter Data Strobe DS Receiver DS DQ[0:15] LDQS,UDQS 6 ...
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... 1HY5DU561622FTP-5 HY5DU561622FTP-4 A10/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 1.1 / Mar. 2008 CKEn /CS, /RAS, /CAS, / 1HY5DU561622FTP-5 HY5DU561622FTP-4 A10/ LDM UDM ADDR ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP 1HY5DU561622FTP-5 HY5DU561622FTP-4 Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622FTP-5 HY5DU561622FTP-4 Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP 1HY5DU561622FTP-5 HY5DU561622FTP-4 Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU561622FTP-5 HY5DU561622FTP-4 Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... 1HY5DU561622FTP-5 HY5DU561622FTP-4 /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... 1HY5DU561622FTP-5 HY5DU561622FTP ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 1.1 / Mar. 2008 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ 1HY5DU561622FTP-5 HY5DU561622FTP-4 < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command 1HY5DU561622FTP-5 HY5DU561622FTP-4 AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... A5 A4 CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved 1HY5DU561622FTP-5 HY5DU561622FTP Burst Length Burst Length Sequential Reserved Reserved Reserved ...
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... HY5DU561622FTP-4 Interleave ...
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... The HY5DU561622FTP supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength. Rev. 1.1 / Mar. 2008 1HY5DU561622FTP-5 HY5DU561622FTP-4 19 ...
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... BA0 MRS Type 0 MRS 1 EMRS * All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.1 / Mar. 2008 1HY5DU561622FTP-5 HY5DU561622FTP RFU* DS DLL A0 DLL enable 0 Enable 1 Diable A6 A1 Output Driver Impedance Control ...
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... DDQ ± the dc value. o (TA Voltage referenced to V Symbol Min 0. 0V 1HY5DU561622FTP-5 HY5DU561622FTP-4 Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.6 2.7 V 2.6 2 0.3 V DDQ - ...
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... Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min); All banks active CKE=<0.2V; External clock on; tCK=tCK(min) 1HY5DU561622FTP-5 HY5DU561622FTP-4 = 0V) SS Speed 4 5 160 150 ...
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... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V 1HY5DU561622FTP-5 HY5DU561622FTP-4 = 0V) SS Max Unit 0.35 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... CCD DPL t 2 DRL Precharge t 9 DAL -0.7 DQSCK t - DQSQ t HPmin QHS t CH min t - QHS 0.4 DQSH t 0.4 DQSL t 0.85 DQSS t 0.4 DS 1HY5DU561622FTP-5 HY5DU561622FTP Max Min Max - 70K 40 70K - 7 5.0 7.0 0.55 0.45 0.55 0.55 0.45 0.55 0.7 -0.7 0.7 0.7 -0.7 0.7 0.4 - 0.45 t HPmin - ...
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... Rev. 1.1 / Mar. 2008 4 Symbol Min Max t 0 0.9 1.1 RPRE t 0.4 0.6 RPST WPRES t 1.5 - WPREH t 0.4 0.6 WPST MRD t 200 - XSC 1tCK t - PDEX + tIS 2tCK tPDEX_RD - + tIS t - 7.8 REFI 1HY5DU561622FTP-5 HY5DU561622FTP-4 5 Unit Note Min Max 0 0.9 1.1 CK 0 0.4 0 200 - CK 4 1tCK - CK + tIS 2tCK - CK + tIS - 7 ...
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... AC CHARACTERISTICS - II tRC Frequency CL (Manual Precharge) 250MHz 4 15 (4.0ns) 200MHz 3 12 (5.0ns) Rev. 1.1 / Mar. 2008 tRC_APCG tRFC tRAS (AUTO Precharge 40ns 14 14 40ns 1HY5DU561622FTP-5 HY5DU561622FTP-4 tRCDRD tRCDWT tRP tDAL Unit tCK tCK 26 ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.1 / Mar. 2008 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50 Ω Zo=50 Ω V REF C =30pF L 1HY5DU561622FTP-5 HY5DU561622FTP-4 Symbol Min Max Unit C 2.0 3 2.0 3 4.0 5 ...
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... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 1.1 / Mar. 2008 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 1HY5DU561622FTP-5 HY5DU561622FTP-4 Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) ...