hy5du561622dlt Hynix Semiconductor, hy5du561622dlt Datasheet
hy5du561622dlt
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hy5du561622dlt Summary of contents
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... DDR SDRAM 256Mb DDR SDRAM HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1 ...
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Revision History Revision No. First Version Release- 1.0 Merged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Rev. 1.0 / Oct. 2004 History HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T Draft Date Remark Oct. 2004 2 ...
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DESCRIPTION The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced ...
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PIN CONFIGURATION x4 x8 VDD VDD NC DQ0 VDDQ VDDQ NC NC DQ0 DQ1 VSSQ VSSQ DQ2 VDDQ VDDQ NC NC DQ1 DQ3 VSSQ VSSQ VDDQ VDDQ VDD VDD ...
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PIN DESCRIPTION PIN TYPE Clock: CK and /CK are differential clock inputs. All address and control input sig- nals are sampled on the crossing of the positive edge of CK and negative edge of CK, /CK Input /CK. Output (read) ...
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FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.0 / Oct. 2004 Write Data Register 2-bit Prefetch Unit 8 ...
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FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.0 / Oct. 2004 Write Data Register 2-bit Prefetch Unit 16 ...
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FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.0 / Oct. 2004 Write Data Register 2-bit Prefetch Unit 32 ...
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SI MPLIFIED COMMAND TRUTH TABLE Command CKEn-1 1,2 Extended Mode Register Set 1,2 Mode Register Set 1 Device Deselect 1 No Operation 1 Bank Active 1 Read 1,3 Read with Autoprecharge 1 Write 1,4 Write with Autoprecharge 1,5 Precharge All ...
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WRITE MASK TRUTH TABLE Function CKEn Data Write 1 H Data-In Mask Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET PDEN POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 1.0 / Oct. 2004 MRS SREF IDLE SREX PDEX AREF ACT POWER DOWN PDEN BST PDEX BANK ACTI VE WRITE READ READAP WITH WITH ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATI ON DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and ...
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Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK LVCMOS ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0) XX0 2 XX1 X00 X01 4 X10 X11 000 001 010 011 8 100 101 110 111 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on V relative Voltage on V relative to V DDQ SS Voltage on inputs relative Voltage pins relative to V ...
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IDD SPECIFICATION AND CONDITIONS Test Conditions Operating Current: One bank; Active - Precharge; tRC=tRC(min); tCK= tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: One bank; Active - ...
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1: Operating current: One bank operation o 1. Typical Case: VDD = 2.5V, T=25 C for DDR200, 266, 333; VDD = 2.6V, T= Worst Case: VDD = 2.7V , ...
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I DD Specification 64Mx4 Parameter Operating Current Operating Current Precharge Power Down Standby Current Idle Standby Current Active Power Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Normal Self Refresh Current Low Power Operating Current ...
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Parameter Operating Current Operating Current Precharge Power Down Standby Current Idle Standby Current Active Power Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Normal Self Refresh Current Low Power Operating Current - Four Bank ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note: ...
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AC CHARACTERISTICS (AC operating conditions unless otherwise noted) DDR400B Parameter Symbol Min Row Cycle Time tRC 55 Auto Refresh Row tRFC 70 Cycle Time Row Active Time tRAS 40 Active to Read with tRCD or Auto Precharge tRAP tRASmin 16 ...
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Parameter Symbol Data-out high-impedance window tHZ 17 from CK,/CK Data-out low-impedance window tLZ 17 from CK, /CK Input Setup Time (fast slew tIS 2,3,5,6 rate) Input Hold Time (fast slew tIH 2,3,5,6 rate) Input Setup Time (slow slew tIS 2,4,5,6 ...
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Note: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock: A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. 3. For command/address input slew rate >=1.0V/ns ...
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I/ O Setup/Hold Delta Inverse Slew Rate Derating. This Derating Table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew ...
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CAPACITANCE o (T =25 C, f=100MHz) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance Note: 1. VDD = min. to max., VDDQ = 2.3V to ...
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PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 22.33 (0.879) 22.12 (0.871) 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 1.0 / Oct. 2004 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE ...