hy5du561622elfp Hynix Semiconductor, hy5du561622elfp Datasheet
hy5du561622elfp
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... DDR SDRAM HY5DU56822E(L)FP HY5DU561622E(L)FP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / June 2006 1 ...
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Revision History Revision No. 1.0 First release 1.1 Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS Rev. 1.1 / June 2006 History HY5DU56822E(L)FP HY5DU561622E(L)FP Draft Date Remark Apr. 2006 June 2006 2 ...
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DESCRIPTION The HY5DU56822E(L)FP, and HY5DU561622E(L)FP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to ...
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PIN CONFIGURATION G ROW AND COLUMN ADDRESS TABLEG ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh Rev. 1.1 / June 2006 HY5DU56822E(L)FP HY5DU561622E(L)FP 32Mx8 16Mx16 4banks 4banks A0 ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input /RAS, /CAS, /WE Input DM Input (LDM,UDM) DQS I/O (LDQS,UDQS Supply Supply DDQ SSQ ...
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FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.1 / June 2006 Write Data Register 2-bit Prefetch Unit ...
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FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE Command /CS Decoder /RAS /CAS /WE ADD Address Buffer BA Rev. 1.1 / June 2006 Write Data Register 2-bit Prefetch Unit 32 ...
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SI MPLIFIED COMMAND TRUTH TABLE Command CKEn-1 1,2 H Extended Mode Register Set 1,2 H Mode Register Set 1 Device Deselect Operation 1 H Bank Active 1 Read H 1,3 Read with Autoprecharge 1 Write H 1,4 ...
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WRITE MASK TRUTH TABLE Function CKEn Data Write 1 H Data-In Mask Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 ...
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SIMPLIFIED STATE DIAGRAM Rev. 1.1 / June 2006 HY5DU56822E(L)FP HY5DU561622E(L)FP 10 ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATI ON DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and ...
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Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS LVCMOS Low Level CKE CMD NOP DM ADDR A10 BA0, BA1 DQS DQ'S T= 200usec Power UP Precharge All VDD and CK stable Rev. 1.1 / June ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0) XX0 2 XX1 X00 X01 4 X10 X11 000 001 010 011 8 100 101 110 111 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on V relative Voltage on V relative to V DDQ SS Voltage on inputs relative Voltage pins relative to V ...
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IDD SPECIFICATION AND CONDITIONS Test Conditions Operating Current: One bank; Active - Precharge; tRC=tRC(min); tCK= tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: One bank; Active - ...
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1: Operating current: One bank operation o 1. Typical Case: VDD = 2.5V, T= Worst Case: VDD = 2. Only one bank is accessed with ...
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IDD Specification 32Mx8 Parameter Operating Current Operating Current Precharge Power Down Standby Current Idle Standby Current Active Power Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Normal Self Refresh Current Low Power Operating Current - ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note: ...
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AC CHARACTERISTICS (note operating conditions unless otherwise noted) DDR400B Parameter Symbol Min Row Cycle Time tRC 55 Auto Refresh Row tRFC 70 Cycle Time Row Active Time tRAS 40 Active to Read with tRCD or ...
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Parameter Symbol Data-out high-impedance window tHZ 10 from CK,/CK Data-out low-impedance window tLZ 10 from CK, /CK Input Setup Time (fast slew tIS 14,16-18 rate) Input Hold Time (fast slew tIH 14,16-18 rate) Input Setup Time (slow slew tIS 15-18 ...
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Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ...
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The pulse duration distortion of on-chip clock circuits; and ...
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SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performance. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for ...
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Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Output (VOUT VSSQ 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ 3 50 Output (VOUT) ...
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CAPACITANCE o (T =25 C, f=100MHz) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance Note: 1. VDD = min. to max., VDDQ = 2.3V to ...
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PACKAGE INFORMATION Rev. 1.1 / June 2006 HY5DU56822E(L)FP HY5DU561622E(L)FP 29 ...