hy5du561622alt Hynix Semiconductor, hy5du561622alt Datasheet - Page 27

• Manufacturer Part Number: hy5du561622alt
• Description: 256m-s Ddr Sdram
• Manufacturer: Hynix Semiconductor

DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
2. Timing patterns
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
2. Timing patterns
Rev. 0.4/ May. 02
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRC = 10*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- DDR266A(133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- DDR266(133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=2, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
changing. lout = 0mA
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
- DDR266A(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
changing once per clock cycle. lout = 0mA
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
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