74F632QC NSC [National Semiconductor], 74F632QC Datasheet

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74F632QC

Manufacturer Part Number
74F632QC
Description
32-Bit Parallel Error Detection and Correction Circuit
Manufacturer
NSC [National Semiconductor]
Datasheet
C 1995 National Semiconductor Corporation
DP8406 (54F 74F632)
32-Bit Parallel Error Detection and Correction Circuit
General Description
The DP8406 device is a 32-bit parallel error detection and
correction circuit (EDAC) in a 52-pin or 68-pin package The
EDAC uses a modified Hamming code to generate a 7-bit
check word from a 32-bit data word This check word is
stored along with the data word during the memory write
cycle During the memory read cycle the 39-bit words from
memory are processed by the EDAC to determine if errors
have occurred in memory
Single-bit errors in the 32-bit data word are flagged and cor-
rected
Single-bit errors in the 7-bit check word are flagged and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location
Dual-bit errors are flagged but not corrected These errors
may occur in any two bits of the 39-bit word from memory
(two errors in the 32-bit data word two errors in the 7-bit
check word or one error in each word) The gross-error
condition of all LOWs or all HIGHs from memory will be
Simplified Functional Block
FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation
TL F 9579
DP8406
DP8406
Device
Package
52-Pin
68-Pin
Byte-Write
detected Otherwise errors in three or more bits of the
39-bit word are beyond the capabilities of these devices to
detect
Read-modify-write (byte-control) operations can be per-
formed by using output latch enable LEDBO and the indi-
vidual OEB
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
Data Bit and Check Bit input latches These will determine if
the failure occurred in memory or in the EDAC
Features
Y
Y
Y
Y
Y
Y
Y
yes
yes
Detects and corrects single-bit errors
Detects and flags dual-bit errors
Built-in diagnostic capability
Fast write and read cycle processing times
Byte-write capability
Guaranteed 4000V minimum ESD protection
Fully
SN74ALS632A thru SN74ALS635 series
pin
0
TRI-STATE
TRI-STATE
through OEB
Output
and
function
3
byte control pins
compatible
RRD-B30M105 Printed in U S A
TL F 9579 – 9
with
May 1991
TI’s

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74F632QC Summary of contents

Page 1

DP8406 (54F 74F632) 32-Bit Parallel Error Detection and Correction Circuit General Description The DP8406 device is a 32-bit parallel error detection and correction circuit (EDAC 52-pin or 68-pin package The EDAC uses a modified Hamming code to generate ...

Page 2

... S Select Pins 0 1 ERR Single Error Flag MERR Multiple Error Flag Connection Diagrams Pin Assignment for LCC and PCC 52-Pin Order Number DP8406QV (74F632QC) See NS Package Number V52A TL F 9579 – 1 54F 74F U L Input HIGH LOW Output ...

Page 3

Connection Diagram (Continued) Pin Assignment for Side Brazed DIP Order Number DP8406D (74F632DC) See NS Package Number D52A Memory EDAC Control Cycle Function Generate Write L L Check Word See Table II for details of check ...

Page 4

Functional Description (Continued) Check Word Bit ...

Page 5

Functional Description (Continued) TABLE IV Read Flag and Correct Function Memory EDAC Control Cycle Function Read Read Flag H L Read Latch Input Data Check H H Bits Read Output Corrected Data H H Syndrome Bits ...

Page 6

Functional Description (Continued) TABLE V Syndrome Decoding (Continued) Syndrome Bits ...

Page 7

Functional Description (Continued) Memory EDAC Control Cycle Function Read Read Flag H L Read Latch Input Data H H Check Bits Read Latch Corrected Data Word into H H Output Latch Modify Modify Write Appropriate Byte ...

Page 8

Block Diagram Timing Waveforms Read Flag and Correct Mode 9579 – 9579– 5 ...

Page 9

Timing Waveforms (Continued) Read Correct and Modify Mode Diagnostic Mode 9579 – 9579 – 7 ...

Page 10

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b Ambient Temperature under Bias b Junction Temperature under Bias b V Pin Potential to CC ...

Page 11

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH ERR PHL t Propagation Delay PLH ERR PHL t Propagation Delay PLH MERR PHL t Propagation Delay PLH ...

Page 12

AC Operating Requirements Symbol Parameter t Setup Time HIGH or LOW before S HIGH (S HIGH (H) Setup Time HIGH s S HIGH before LEDBO HIGH 0 t (H) Setup Time HIGH s LEDBO ...

Page 13

Physical Dimensions inches (millimeters) 52-Lead Side-Brazed Ceramic Dual-In-Line Package (D) NS Package Number D52A 52-Lead Plastic Chip Carrier (Q) NS Package Number V52A 13 ...

Page 14

Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 ...

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