74F632QC NSC [National Semiconductor], 74F632QC Datasheet - Page 4

• Manufacturer Part Number: 74F632QC
• Description: 32-Bit Parallel Error Detection and Correction Circuit
• Manufacturer: NSC [National Semiconductor]

Check Word
Functional Description
The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit
H
L
If the parity of one or more of the check groups is incorrect
an error has occurred and the proper error flag or flags will
be set LOW Any single error in the 32-bit data word will
change the state of either three or five bits of the 7-bit
check word Any single error in the 7-bit check word chang-
es the state of only that one bit In either case the single
error flag (ERR) will be set LOW while the dual error flag
(MERR) will remain HIGH
Any 2-bit error will change the state of an even number of
check bits The 2-bit error is not correctable since the parity
tree can only identify single-bit errors Both error flags are
set LOW when any 2-bit error is detected
Three or more simultaneous bit errors can cause the EDAC
to believe that no error a correctable error or an uncorrect-
able error has occurred and will produce erroneous results
in all three cases It should be noted that the gross-error
conditions of all LOWs and all HIGHs will be detected
As the corrected word is made available on the data I O
port (DB
through CB
syndrome error code can be used to locate the bad memory
chip See Table V for syndrome decoding
READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS
The ’F632 device is capable of byte-write operations The
39-bit word from memory must first be latched into the Data
Bit and Check Bit input latches This is easily accomplished
by switching from the read and flag mode (S
to the latch input mode (S
then make any corrections if necessary to the data word
and place it at the input of the output data latch This data
word must then be latched into the output data latch by
taking LEDBO from a LOW to a HIGH
e
e
CB
CB
CB
CB
CB
CB
CB
Bit
32-Bit Data Word
LOW Voltage Level
HIGH Voltage Level
0
1
2
3
4
5
6
0
through DB
6
0
1
0
1
2
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
) presents a 7-bit syndrome error code This
X
X
X
X
X
Total Number of Errors
X
X
X
X
X
X
X
X
31
X
X
X
X
X
) the check word I O port (CB
1
e
X
X
X
H S
X
X
X
X
X
7-Bit Check Word
0
X
X
X
e
(Continued)
X
X
X
H) The EDAC will
1
0
0
1
1
0
2
X
X
X
e
H S
X
X
X
TABLE II Parity Algorithm
TABLE III Error Function
0
X
X
X
e
X
X
X
L)
0
X
X
X
32-Bit Data Word
4
X
X
X
Byte control can now be employed on the data word
through the OEB
DB
OEB
DB
disable the output and the user can modify the byte If a
LOW is placed on the byte control then the original byte is
allowed to pass onto the data bus unchanged If the original
data word is altered through byte control a new check word
must be generated before it is written back into memory
This is easily accomplished by taking controls S
LOW Table VI lists the read-modify-write functions
DIAGNOSTIC OPERATIONS
The ’F632 is capable of diagnostics that allow the user to
determine whether the EDAC or the memory is failing The
diagnostic function tables will help the user to see the possi-
bilities for diagnostic control In the diagnostic mode
(S
latch while the data input latch remains transparent This
lets the user apply various data words against a fixed known
check word If the user applies a diagnostic data word with
an error in any bit location the ERR flag should be LOW If a
diagnostic data word with two errors in any bit location is
applied the MERR flag should be LOW After the check
word is latched into the input latch it can be verified by
taking OECB LOW This outputs the latched check word
The diagnostic data word can be latched into the output
data latch and verified By changing from the diagnostic
mode (S
diagnostic data word Also the syndrome bits can be pro-
duced to verify that the EDAC pinpoints the error location
Table VII lists the diagnostic functions
e
ERR
H
X
X
X
L
L
L
L
L
1
0
24
H) the user can verify that the EDAC will correct the
e
–DB
2
–DB
X
X
X
Error Flags
controls DB
L S
1
7
31
X
X
X
e
0
(byte 0) OEB
(byte 3) Placing a HIGH on the byte control will
L S
e
X
X
X
H) the check word is latched into the input
0
0
X
X
X
e
MERR
16
through OEB
H
H
H
L
L
L
H) to the correction mode (S
– DB
X
X
X
23
X
X
X
1
controls DB
(byte 2) and OEB
X
X X
X X X
3
X X X X
controls OEB
X
Data Correction
Not Applicable
Correction
Correction
Interrupt
Interrupt
Interrupt
X
X X X
X X X X X X
X X X X X X X X
8
X
–DB
15
X
X
X X
3
0
1
1
(byte 1)
controls
controls
e
and S
H S
X X X
X X
0
0
X
X