cxa3572r Sony Electronics, cxa3572r Datasheet
cxa3572r
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cxa3572r Summary of contents
Page 1
... Driver/Timing Generator for Color LCD Panels Description The CXA3572R designed to drive the color LCD panel ACX306/312. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals and a VCO onto a single chip. This chip has a built-in serial interface ...
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... Block Diagram ATT 25 ATT ATT RPD SEN 32 SCK 33 SDAT SERIAL I PLL 35 XCLR COUNTER 36 POF PICTURE H. FILTER – 2 – CXA3572R ...
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... SDAT I Serial data input Vertical sync signal input 35 XCLR I Power-on reset capacitor connection (timing output block) LCD panel power supply on/off 36 POF O (Leave this pin open when not using this function.) Description – 3 – CXA3572R Input pin for open status L ...
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... H clock pulse 1 output 43 HCK2 O H clock pulse 2 output 44 HST O H start pulse output 45 V — Digital 3.0V power supply DD 46 WIDE O WIDE pulse output 47 DWN O Up/down inversion switching signal output 48 V — Digital 3.0V GND SS Description – 4 – CXA3572R Input pin for open status ...
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... Low output in power saving mode. 100k 14 Analog 12.0V power supply and PSIG output DC voltage setting. 200k Connect a 0.01µF capacitor between 16 this pin and GND1. When using a SIG.C of other than 200k 10p Vcc2/2, input the SIG.C voltage from an external source. No connection. – 5 – CXA3572R Description ...
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... During input to the sync separation circuit, input via a capacitor. DA output. 80k Outputs the serial data converted to DC voltage. The current driving capacity is ±1.0mA (max.). 15p 25k REF output. The current driving capacity (sink) is 1.6mA (max.). 100k – 6 – CXA3572R Description ...
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... GND side of the external resistor and the GND1 pin as close as possible. 1k 100k Phase comparator output. Analog 3.0V GND. 1 20k Serial clock, serial load and serial data inputs for serial communication. – 7 – CXA3572R Description resistor (tolerance ±2%, ...
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... Digital block outputs Vss 35 32 Digital block system reset, and serial 31 33 clock, serial load and serial data inputs for serial communication. Vss 34 Vertical sync signal input. Vss Digital 3.0V power supply. Digital 3.0V GND. Test. Leave this pin open. – 8 – CXA3572R Description ...
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... In the condition without sync input, adjust so that the HDO pulse output frequency is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz. Setting 3. Canceling power saving mode The power-on default is power saving mode, so clear (set all “1”) serial data PS0 and SYNC GEN > 10µ System reset – 9 – CXA3572R ...
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... SYST SLFR SL4096 SLFL 0 (0) (0) (0) (0) SLMBK POSITION (100000/LSB) (0) 0 S/H POSITION (000/LSB POSITION (100/LSB) 0 TEST4 (00000000/LSB) – 10 – CXA3572R DATA (10000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (1000000/LSB) (1000000/LSB) -1 (0000000/LSB) -2 (0000000/LSB) (1000000/LSB) (1000000/LSB) COLOR (1000000/LSB) HUE (1000000/LSB) (10000000/LSB) (100000/LSB) ...
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... V22 During Y/color difference V23 input V23 During RGB input During Y/color difference V24 input V24 During RGB input V25 During no input V27 V28 VSIG.C – 11 – CXA3572R 2 = 12.0V, see page 10 for the DAC) Min. Typ. Max. Unit 1.0 3 1.0 3 — ...
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... SYNC level of Y (G) on SYNC signal. Measurement conditions INPUT SEL = 0 2 (–6dB Attenuate OFF) INPUT SEL = 1 2 (–6dB Attenuate ON) 1 INPUT SEL = 0 (–6dB Attenuate OFF INPUT SEL = 1 (–6dB Attenuate ON) 2 – 12 – CXA3572R Min. Typ. Max. Unit 0.35 0.4 0.15 0.2 0.245 0.311 0.7 0.3 Vp-p 0.490 0.622 0.35 ...
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... –1.2mA 2 4.0mA –0.6mA 2 2.0mA OL – 13 – CXA3572R 2.7 to 3.6V Max. Unit Applicable pins 0 0 150 3 µA (pull-down) 1.0 1.0 4 1 ...
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... Set U-BRT = 00h, measure the non-inverted black limit level at TP12 00h when BLK-LIM = 00h and 3Fh, and assume the difference from the output DC voltage and V BL 3Fh respectively. – 14 – CXA3572R Min. Typ. Max. Unit –6 – — ...
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... PIC-G = 00h and 1Fh, respectively. Input SG4 (160mVp-p) to TP23 and TP24, and assume the output amplitude at TP8 and TP10 when COLOR = 00h, 40h and 50h as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) GC2 = 20 log (V3/V2) – 15 – CXA3572R Min. Typ. Max. Unit 0.3 0.6 1.0 V — — ...
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... GAMMA1 = GAMMA2 = 3Fh as V3 log (V1/V2 log (V3/V2) Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when 1 = 00h and 1 = 7Fh from the IRE level of the input signal 00h: V 1MN 1 = 7Fh: V 1MX – 16 – CXA3572R Min. Typ. Max. Unit 0.85 1.00 1.15 0.41 0.51 0.61 0.15 0.19 0.23 — ...
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... DWN, WIDE, VCK, VST, TEST, EN, VDO, HDO, POF and RGT output pins (See Fig. 1.) Measure HCK1/HCK2. 120pF load (See Fig. 2.) Measure the HCK1/HCK2 duty. 120pF load – 17 – CXA3572R Min. Typ. Max. Unit 100 — — IRE — — 50 – ...
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... SDAT D15 D14 D13 D12 D11 D10 ts1 th1 SCK tw1H SEN ts0 Fig. 3. Serial transfer block measurement conditions 90% 10% T tTHL Fig. 2. Cross-point time difference measurement conditions tw1L – 18 – CXA3572R T 50 D15 50% 50% th0 tw2 ...
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... Sine wave video signal; frequency and amplitude variable SG3 25µs SG4 SG5 25µs Waveform 4.7µ Horizontal sync signal 1H 10µs 10µs – 19 – CXA3572R 3.0Vp-p Amplitude variable 0.1Vp-p 0.1Vp-p High level variable 0V Horizontal sync signal 3V Low level variable Horizontal sync signal ...
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... SG No. Horizontal sync signal (CSYNC) SG6 Sine wave video signal SG7 Horizontal sync signal (CSYNC) SG8 Waveform 4.7µ 4.7ns 1H – 20 – CXA3572R 50mVp-p 0.1Vp-p 0.15Vp-p ...
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... TP33 TP32 TP31 TP27 TP26 TP25 43k TP6 TP10 TP8 – 21 – CXA3572R 1µ 0.01µ TP24 24 B/B-Y 0.01µ TP23 R/R-Y 23 +3V 0.01µ TP22 G Vcc1 0.01µ 20 TP20 OSD G TP19 OSD R 19 ...
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... The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the R signal to Pin 23. the R-Y signal to Pin 23. The G signal is input to Pin 22, the B signal to Pin 24, the R signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. – 22 – CXA3572R correction, 1/3) and Vth2 (Vcc1 2/3). ...
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... SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS4 SHS5 SHS6 SHS1 Through Through Through Output Output Input Fig. 2 – 23 – CXA3572R Serial data settings Input Fig. 3 ...
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... BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously goes to BLACK-LIMITER level output. RGB IN 1H inverted signal (internal) Black frame display signal (internal) PSIG OUT RGB OUT Set by BLACK-LIMITER Set by PSIG-BRIGHT Set by BLACK-LIMITER – 24 – CXA3572R BLACK-LIMITER SIG.C BLACK-LIMITER BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER BLACK-LIMITER ...
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... The serial data PS0 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the “Description of Serial Control Operation” and “Power supply and power saving sequence” items. Min: 25MHz Max: 30MHz VCO-Fine setting range (255 steps) – 25 – CXA3572R VCO-Coarse setting (7 steps) ...
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... Power supply and power saving sequence Power-on for the CXA3572R and the LCD panel should be performed in the following order. Power-on LCD V DD (LCD panel 12V (analog 12V block (analog 3V block (digital 3V block) 1 Power saving setting Power saving ...
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... AC driving of LCD panels during no signal The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the SYNC IN (Pin 25) and VD (Pin 34) pins. Black display 453 dots 6 lines Display area 228 lines 6 lines Black frame display – 27 – CXA3572R ...
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... IC and is ignored bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data. SDAT SCK SEN T T > 10µ System reset A: ADDRESS Serial transfer timing – 28 – CXA3572R D: DATA ...
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... SLFL SYST SLFR SL4096 0 (0) (0) (0) (0) SLMBK (0) H POSITION (100000/LSB) 1 (0) 0 S/H POSITION (000/LSB POSITION (100/LSB) 0 TEST4 (00000000/LSB) – 29 – CXA3572R DATA (10000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (1000000/LSB) (1000000/LSB) -1 (0000000/LSB) -2 (0000000/LSB) (1000000/LSB) (1000000/LSB) COLOR (1000000/LSB) HUE (1000000/LSB) (10000000/LSB) (100000/LSB) ...
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... This adjusts the phase during Y/color difference input. Adjustment from LSB MSB increases the amplitude MSB decreases the amplitude MSB increases the output voltage. MSB increases the gain. MSB advances the phase. – 30 – CXA3572R MSB decreases the LSB lowers the MSB lowers the ...
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... See the AC Characteristics for the output level (RGB input/no load/typ — 1.5MHz 2.1MHz 2.7MHz 3.5MHz 4.1MHz 4.6MHz 5.2MHz – 31 – CXA3572R MSB increases the MSB increases the MSB lowers the MSB raises the gain. ...
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... Power saving 1 Normal operation MSB raises the output voltage level. Input signal level 0.35Vp-p or less, 0.5Vp-p or less with sync 0.35Vp-p or more, 0.5Vp-p or more with sync Input connection method Input via a coupling capacitor Input level 3Vp-p positive or negative polarity – 32 – CXA3572R ...
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... This switches the time until the picture is displayed after power saving is canceled. PONF Mode 0 12 fields 1 4 fields • TEST2 (Default: 0) This is the test mode. Set to “1”. TEST2 Mode 0 Test mode 1 Normal operation • SLNTPL (Default: 0) This switches between NTSC and PAL mode. SLNTPL Mode 0 NTSC 1 PAL – 33 – CXA3572R ...
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... External VSYNC input • SLSYP (Default: 0) This switches the input sync signal polarity. When performing sync separation with the internal sync separation circuit from YonSYNC or GonSYNC, set this to “0”. SLSYP HD/CSYNC, VSYNC polarity 0 Positive polarity 1 Negative polarity – 34 – CXA3572R ...
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... SLFR (Default: 0) This function inverts the and PSIG output signal polarities every field. Normally set to 1H inversion. SLFR Polarity inversion cycle 0 1H inversion 1 1-field inversion Position 2.0µs 2.9µs 2.0µs 2.0µs 3.6µs 2.0µs – 35 – CXA3572R ...
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... These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. HSYNC HDO HP: 100000 (LSB) Default HP: 000000 (LSB) HP: 111111 (LSB) 30 steps (fH) 31 steps (fH) HP: 00000 (LSB) Default HP: 11111 (LSB) 31 steps (124fH) – 36 – CXA3572R ...
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... TEST4 (Default: 00000000/LSB) This is the test mode. Set to 00000000/LSB (8 bits). VP: 01000 (LSB) Default VP: 00000 (LSB) VP: 11111 (LSB) 8 steps (8H) 23 steps (23H) 4 steps 3 steps (4fH) (3fH) – 37 – CXA3572R SBP: 000 (LSB) SBP: 100 (LSB) SBP: 111 (LSB) ...
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... PSIG DC DET 33µ To LCD Panel – 38 – CXA3572R 0.1µ 25 0.1µ B/B-Y B/B-Y 24 0.1µ R/R-Y R/R-Y 23 0.1µ 22 G/Y G/Y +3V 21 Vcc1 (Analog) 0.1µ 20 OSD G 19 OSD R 33µ ...
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... The voltages applied to the power supply pins should be as follows GND1 = GND2 (13) Be sure to connect the damping resistor pattern in order to reduce impedance as much as SS (max.) or less.) or lower than V to I/O pins ROUT, GOUT, BOUT, PSIGOUT and COM output. – 39 – CXA3572R should not be SS ...
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... A 13 (0.22 0.2 1.5 – 0.1 0.13 M 0.1 ± 0.1 0.18 ± 0.03 DETAIL B: PALLADIUM NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LQFP-48P-L01 LEAD TREATMENT P-LQFP48-7x7-0.5 LEAD MATERIAL PACKAGE MASS – 40 – CXA3572R B + 0.05 0.127 – 0.02 0.1 S EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g Sony Corporation ...