cxa3522r Sony Electronics, cxa3522r Datasheet
cxa3522r
Related parts for cxa3522r
cxa3522r Summary of contents
Page 1
... Driver/Timing Generator for Color LCD Panels Description The CXA3522R designed to drive the color LCD panel ACX306. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc ...
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... SUB-BRT R SUB-BRT POL SW PLL COUNTER DL1 HUE VCK GEN HUE COLOR CLP V COUNTER DA REF Buf Buf GND1 – 2 – CXA3522R +12.0V +12.0V PSIG- BRT 36 PSIG- Buf BRIGHT 35 POL SW 34 Buf 33 Buf 32 31 Buf 30 29 SIG.C GND2 ...
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... R DC DET O R signal DC voltage feedback circuit capacitor connection 34 R OUT O R signal output DET O G signal DC voltage feedback circuit capacitor connection 36 G OUT O G signal output — Analog 12.0V power supply CC Description – 3 – CXA3522R Input pin for open status L H ...
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... I H filter input (for using internal sync separation) 70 B/B-Y I B/B-Y signal input 71 G/Y I G/Y signal input 72 R/R-Y I R/R-Y signal input DWN: DOWN SCAN and UP SCAN, RGT: RIGHT SCAN and LEFT SCAN H: pull-up processing, L: pull-down processing Description – 4 – CXA3522R Input pin for open status ...
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... GND1 51k GND1 – 5 – CXA3522R Description Amplifies and outputs the sync portion of the video signal input to FIL IN (Pin 69). Sync separation circuit input. Inputs the FIL OUT (Pin 2) output signal via a capacitor. Sync separation output. Positive polarity output in open collector format ...
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... 140k 200 30 140k 10pF GND1 – 6 – CXA3522R Description Connect a resistor between this pin and GND1 to control the internal LPF and trap frequencies. Connect a 33k resistor (tolerance ±2%, temperature characteristics ±200ppm or less). This pin is easily affected by external noise, so make the ...
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... GND3 50k 58 59 50k GND1 – 7 – CXA3522R Description Smoothing capacitor connection for the feedback circuit and PSIG output DC level control. Connect a low-leakage capacitor and PSIG signal outputs. The DC level is controlled to match the SIG.C pin voltage. ...
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... GND1 200 71 72 GND1 – 8 – CXA3522R Description Analog 3.0V power supply. H filter input. Input the video signal via a capacitor. In Y/color difference input mode, input the Y signal to Pin 71, the B-Y signal to Pin 70, and the R-Y signal to Pin 72. In RGB input mode, input the ...
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... V SS – 9 – CXA3522R Description Digital 3.0V GND. Digital 3.0V power supply. Composite sync/horizontal sync signal input, and serial clock, serial load and serial data inputs for serial communication. Vertical sync signal input. Oscillation circuit output. Oscillation circuit input. ...
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... Test Pin Description Pin Pin Symbol No. voltage 13 TST1 40 TST3 44 TST4 49 TST7 — 50 TST8 51 TST9 52 TST10 28 TST2 47 TST5 — 48 TST6 56 TST11 Equivalent circuit Test. Leave these pins open. Test. Connect to GND. – 10 – CXA3522R Description ...
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... SLOV (0) SLEXVD (0) SLFR ( SLSH2 (1) SLSH0 ( SLSH1 (1) SB-POSITION(100 – 11 – CXA3522R DATA LSB USER-BRIGHT (01000110/LSB) SUB-BRIGHT R (10001010/LSB) SUB-BRIGHT B (10001010/LSB) CONTRAST (00111111/LSB) (10011111/LSB) (10011111/LSB) -2 (11111111/LSB) -1 (11111111/LSB) PSIG-BRIGHT (1011111/LSB) COM-DC (10000000/LSB) ...
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... V31 V33 V35 V38 V69 V70 During Y/color difference input V70 During RGB input V71 V72 During Y/color difference input V72 During RGB input 1.5mA V57 V58 V59 – 12 – CXA3522R =3.0V 12.0V Min. Typ. Max. Unit 27.0 37.0 mA 3.8 5.0 mA 0.90 1.3 mA 23.0 30 ...
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... –0.25mA 2 2mA –0.5mA 2 4mA –1mA 2 1.5mA –1.25mA V – 0 High impedance status – 13 – CXA3522R = 2.7 to 3.6V Applicable Typ. Max. Unit pins 1.0 µA 4 1.0 µA 3.0 µ ...
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... Set U-BRT = FFh, measure the inverted and non-inverted black limit level at TP36 when BLK-LIM = 00h and 1Fh, and assume the difference from the output DC voltage and V 2, respectively – 14 – CXA3522R = 0V, SW2 = ON, SW4 = ON, SS Min. Typ. Max. Unit ...
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... Input SG4 (50mVp-p) to TP70 and TP72, and assume the output amplitude at TP32 and TP34 when COLOR = 00h, 80h and FFh as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) GC2 = 20 log (V3/V2) – 15 – CXA3522R Min. Typ. Max. Unit ±1.2 ±0.6 ± ±0.6 ±1.2 ±1.8 ...
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... TP32, TP34 and TP36. Assume the output amplitude when GAMMA1 = FFh as V1, when GAMMA1 = 3Fh as V2, and when GAMMA1 = GAMMA2 = 3Fh as V3 log (V1/V2 log (V3/V2) Input SG6 to TP69 and measure the output amplitude at TP2. – 16 – CXA3522R Min. Typ. Max. Unit 0.85 1.00 1.15 0.41 0.51 0.61 0.15 ...
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... Input SG6 to TP69 and measure the propagation delay time of the rise and fall at TP2 from TP69. Set SW2 = OFF, input SG8 to TP3, and measure the propagation delay time of the rise and fall at TP4 from TP3. – 17 – CXA3522R Min. Typ. Max. Unit ±1.0 ±1 µ ...
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... Measure the transition time of each output. 40pF load: DWN, EN, VCK, VST and RGT output pins (See Fig. 2.) Measure HCK1/HCK2. 90pF load (See Fig. 3.) Measure the HCK1/HCK2 duty. 90pF load – 18 – CXA3522R Min. Typ. Max. Unit 150 ns 150 150 ns 150 210 ns ...
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... SDTA D15 D14 D13 D12 D11 D10 ts1 th1 SCK tw1H SEN ts0 Fig. 4. Serial transfer block measurement conditions 90% 10% tTHL T Fig. 3. Cross-point time difference measurement conditions tw1L – 19 – CXA3522R T 50 D15 50% 50% th0 tw2 ...
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... Sine wave video signal; frequency and amplitude variable SG3 25 s SG4 SG5 Waveform 4 – 20 – CXA3522R 3.0Vp-p Amplitude variable Horizontal sync signal 0.1Vp-p 0.1Vp-p High level variable 0V Horizontal sync signal 3V Low level variable Horizontal sync signal ...
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... SG No. Horizontal sync signal (CSYNC) SG6 Sine wave video signal SG7 Horizontal sync signal (CSYNC) SG8 Waveform 4 4 – 21 – CXA3522R 50mVp-p 0.1Vp-p 0.15Vp-p ...
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... TP5 TP6 TP7 TP11 TP12 TP14 TP15 TP4 – 22 – CXA3522R TP39 400pF +12V SW39 A +12V 0 TP36 G OUT 0 DET 35 SW36 10 34 ...
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... Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER. R-Y signal to Pin 72. Pin 72, CSYNC/HD to Pin 5, and VD to Pin 10. – 23 – CXA3522R 1 1/3) and Vth2 (V 1 2/3). CC ...
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... SH2: G signal SH pulse Through Through Through SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1,2,3,4,5,6: Serial data settings SHS4 SHS5 SHS6 Through Through Through Output Output Input Fig. 2 – 24 – CXA3522R Input Fig. 3 ...
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... BLACK-LIMITER level output. RGB IN 1H inverted signal (internal FRP) Black frame display signal (internal PRG) PSIG OUT RGB OUT 2 + GND2)/2 (or the voltage input to SIG.C CC Set by BLACK-LIMITER Set by PSIG-BRIGHT Set by BLACK-LIMITER – 25 – CXA3522R BLACK-LIMITER SIG.C BLACK-LIMITER BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER BLACK-LIMITER ...
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... The serial data PS0, PS1, PS2, PS4 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the "Description of Serial Control Operation" and "Power Supply and Power Saving Sequence" items. – 26 – CXA3522R ...
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... FIL IN (Pin 69) pin or from the CSYNC/HD (Pin 5) and VD (Pin 10) pins. It also runs freely when there is no sync signal during 281H (NTSC) and 331H (PAL) of display system. Respective cycles are 281H (NTSC) and 331H (PAL 453 DOTS Display area Black frame display – 27 – CXA3522R Black display 6 LINES 228 LINES 6 LINES ...
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... SLOV (0) SLEXVD (0) SLFR (0) SLSYP ( (0) (0) ( (0) ( SLSH2 (0) SLSH1 (0) SLSH0 ( SB-POSITION (100/LSB – 28 – CXA3522R D: DATA DATA LSB (10000000/LSB) (10000000/LSB) (10000000/LSB) CONTRAST (10000000/LSB) (10000000/LSB) (10000000/LSB) -2 (00000000/LSB) -1 (00000000/LSB) (1000000/LSB) COM-DC (10000000/LSB) COLOR (10000000/LSB) HUE ...
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... MSB increases the amplitude MSB increases the amplitude MSB increases the amplitude MSB increases the output voltage. MSB increases the gain. MSB advances the phase. – 29 – CXA3522R LSB lowers the point. LSB lowers the point. MSB lowers the ...
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... PICTURE-GAIN This adjusts the picture gain during Y/color difference input. Adjustment from LSB When not using the picture function (OFF), set PICTURE-GAIN: 00000 (LSB). MSB raises the output voltage level. See the – 30 – CXA3522R MSB raises the gain. ...
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... Supply and Power Saving Sequence". The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. D0 Normal operation 1 Respective outputs and corresponding output blocks are stopped. Mode (SYNC GEN) Mode (PS0, PS1, PS2, PS4) – 31 – CXA3522R ...
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... LCD power-on PS1 0 PS2 0 PS4 0 (1) SYNC GEN 0 Fig. 1 – 32 – CXA3522R Default LCD display Power-on PS OFF Power-off power-off PS0 0 LCD power-off PS1 0 PS2 0 PS4 0 (1) SYNC GEN 0 Power supply CXA3522R LCD Signal Fig. 2. System block diagram ...
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... LCD display PS PS OFF PS ON Power-off power-off PS0 0 PS0 1 LCD power-off PS1 0 PS1 1 PS2 0 PS2 1 PS4 0 (1) PS4 1 SYNC GEN SYNC GEN Power supply 3V output POF pin VV DD CXA3522R SW LCD Signal Fig. 2. System block diagram ...
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... SYNC GEN PS0 0 PS0 1 PS0 1 PS1 0 PS1 1 PS1 1 PS2 0 PS2 0 PS2 1 PS4 0 (1) PS4 0 (1) PS4 1 SYNC GEN SYNC GEN SYNC GEN Power supply 3V output POF pin VV DD CXA3522R SW LCD Signal Fig. 2. System block diagram 4 ...
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... HD/Pins 10 and 5) input. Set to "0" during external CSYNC/Pin 5 input. D6 Mode 0 Other than during external vertical sync signal input 1 External vertical sync signal input D1 Output polarity (VDO) 0 Positive polarity 1 Negative polarity – 35 – CXA3522R ...
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... These set the H position. The horizontal display position is switched by adjusting the HST pulse position using the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 1fH increments. Horizontal sync signal HST Clamp position 2. 2 steps 31 steps (32fH) (31fH) – 36 – CXA3522R 2 s HP: 000000 (LSB) HP: 100000 (LSB) HP: 111111 (LSB) ...
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... Adjustment is possible in 1 bit = 4fH increments. Horizontal sync signal HDO 8 steps 23 steps (8H) (23H) 4 steps (3fH) (4fH) 31 steps (124fH) – 37 – CXA3522R VP: 00000 (LSB) VP: 01000 (LSB) VP: 11111 (LSB) SBP: 000 (LSB) SBP: 100 (LSB) SBP: 111(LSB) 3 steps (3fH) HDP: 00000 (LSB) HDP: 11111 (LSB) ...
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... LCD Panel To Serial Controller – 38 – CXA3522R +12V 22k IN 22k +12V Buff Sample PSIG buffer circuit 0.68 F +12V OUT 0. DET ...
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... LCD Panel To Serial Controller – 39 – CXA3522R +12V 22k IN 22k +12V Buff Sample PSIG buffer circuit 0.68 F +12V OUT 0. DET ...
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... GND1, GND2 and GND3 pins to the lowest potential applied to this IC; do not SS leave these pins open. The voltages applied to the power supply pins should be as follows GND1 = GND2 = GND3 SS ) pattern in order to reduce impedance as much as possible lower than V to I/O pins – 40 – CXA3522R should not be SS ...
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... EIAJ CODE P-LQFP72-10X10-0.5 JEDEC CODE 72PIN LQFP (PLASTIC) 12.0 ± 0.3 10.0 ± 0.2 0.65 ± 0 0.2 ± 0.08 0.08 M 0.1 ± 0.1 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-72P-L111 LEAD MATERIAL PACKAGE MASS – 41 – CXA3522R 14.5 ± 0.2 0.15 ± 0.05 0.1 EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g Sony Corporation ...