ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 18

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

18
(without thoroughly understanding your PCB layout power
up dynamics the safest course is to make short
connections and do not to add decoupling capacitors to
these pins).
When Pin 7 (PECLTP) and Pin 8 (PECLQU) are connected
to 1/3 VCC and 2/3 VCC use >20kΩ resistors and
connect to the proper decoupled VCCD and GNDD. For
Pin 7 (PECLTP) use Pin 19 VCCD and Pin 15 GNDD, do
not add decoupling capacitors to Pin 7. For Pin 8
(PECLQU use Pin 19 VCCD and Pin15 GNDD, do not add
decoupling capacitors to Pin 8. When Pin 25 (DUPLEX)
and Pin 27 (SPEED) are connected to VCC/2 use the
internal 80kΩ resistor pair by leaving the pin open. Do not
add external resistors or decoupling capacitors these
pins.
When Pin 4 AD4LIW is connected to 1/3 and 2/3 VCC use
>20kΩ resistors and connect to the proper decoupled
VCCD and GNDD. When Pin 4 AD4LIW is connected to
ground use Pin 15 GNDD. When Pin 4 AD4LIW is
connected to VCC use Pin 19 VCCD and do not add
decoupling capacitors to pin 4 AD4LIW. Pull Pin 40
BCKPLINK up and down (One and Zero) through a 10K
resistor connected to either Pin 19 VCCD or Pin 15
GNDD.
Thus the ML6652 is designed to self-configure in stand
alone applications as well as act under the control of a
microprocessor or other control device in a managed
setting.
OPERATING MODES
b)
c)
control: (Note: When Pin 4 (AD4LIW) Pin 5 (AD
32) and Pin 6 (AD10) are connected to 1/3 VCC
and 2/3 VCC use >20K ohm resistors and connect
to the proper decoupled Pin 19 VCCD and Pin 15
GNDD do not add decoupling capacitors to Pin 4,
5 or 6.)
i)
ii) Pin 5 (AD 32)
iii) Pin 6 (AD10)
iv) Pin 13 (TPOUTOFF#)
v)
vi) Pin 24 (PWRDWN#)
vii) Pin 40 (BCKPLINK)
i)
ii) Pin 42 (FOINSPD)
iii) Pin 43 (TPANDT)
iv) Pin 44 (FOANDT)
The following pins are available at all times for
LED Status indicators are available:
Pin 4 (AD4LIW)
Pin 14 (FOOUTOFF#)
Pin 41 (TPINSPD)
January 2004
TRANSPARENT MODE
Twisted Pair Input/Output Interface
Two operating modes are available for the twisted pair
differential inputs TPINP (pin 10)/TPINN (pin 11) and the
differential output pair TPOUTP (pin 1)/TPOUTN (pin 3)
selected by the input configuration pin PECLTP (pin 7) or
by the setting of bit <30.3> in management register 30.
In twisted pair interface mode, the inputs form a
differential pair that receives twisted pair positive and
complementary signals and the outputs form a differential
current output pair that drives MLT-3 encoded 100BASE
data, Manchester encoded 10BASE-T data or NLPs
during 10Mbps mode, and FLP bursts during Auto-
Negotiation into a network coupling 1:1 transformer.
To communicate between two fiber optic sources, the
twisted pair input and output can be configured as PECL/
LVPECL interface compatible with the configuration pin
PECLTP or by setting bit <30.3> high. In this mode, both
the input differential pair and the output differential pair
provide PECL/LVPECL compatible interface positive and
complementary levels.
The preferred mode of operation is twisted pair compatible
signal levels. The default mode of operation is set by
PECLTP (pin 7).
Fiber Optic input/Output Interface
Two modes of operation are available for the fiber optic
inputs FOINP (pin 33), FOINN (pin 32) and the fiber optic
outputs IOUT (pin 21) and IOUT# (pin 22) selected by
input control pin PECLQU (pin 8) or by the setting of bit
<30.7> in management register 30.
PECLQU is a four level input and when set at VCC/3 by
an external resistor network the two outputs IOUT/IOUT#
form a differential output pair that are AC coupled to a
fiber optic PMD module. The differential current output
pair output NRZI encoded 100BASE-FX or 100BASE-SX
symbols in 100Mbps mode. They output Manchester
encoded 10BASE-FL data or Optical Idle (OPT_IDL) in
10Mbps mode and FLNP bursts during Auto-Negotiation.
IOUT and IOUT# require external pull-up resistors to VCC
and must be AC coupled to a fiber optic PMD module. A
resistor network is required to establish the common mode
voltage at the inputs to the PMD module.
With PECLQU input level of VCC, 2VCC/3, or 0Volts, the
two outputs become independent and are defined as the
Fiber Optic Interface Mode. In this mode, IOUT becomes
a data output to a fiber optic LED driver connecting to the
cathode. The data is NRZI encoded 100BASE-FX or
100BASE-SX symbols in 100Mbps mode. The data is
Manchester encoded 10BASE-FL or OPT_IDL in 10Mbps
mode and FLNP Bursts during Auto-Negotiation.
IOUT# is optionally used to provide current peaking. If
current peaking is implemented, typically a 1kΩ off-chip
Final Datasheet
DS6652-F-02
ML6652