mx26l6419 Macronix International Co., mx26l6419 Datasheet
mx26l6419
Related parts for mx26l6419
mx26l6419 Summary of contents
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... Buffer Command) • Program/Erase Endurance cycles: 100 cycles GENERAL DESCRIPTION The MXIC's MX26L6419 series MTP use the most ad- vance 2 bits/cell Nbit technology, double the storage ca- pacity of memory cell. The device provide the high den- sity MTP memory solution with reliable performance and most cost-effective ...
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... Device Power Supply GND Device Ground Note: ACC pin and VPEN pin are not allowed to be op- eration at the same time. P/N:PM0946 MX26L6419 (x16 only) 36 Normal Type MX26L6419 A16 VCCQ ...
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... BLOCK DIAGRAM CE CONTROL OE INPUT WE LOGIC RESET ADDRESS LATCH A0-A21 AND BUFFER Q0-Q15 P/N:PM0946 MX26L6419 PROGRAM/ERASE HIGH VOLTAGE MTP ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV DATA LATCH PROGRAM DATA LATCH I/O BUFFER 3 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA ...
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... MTP memory reads erases and writes in-system via the local CPU. All bus cycles to or from the MTP memory conform to standard microprocessor bus cycles. 3FFFFF 1FFFFF P/N:PM0946 A21~A0 64-Kword Block 3F0000 . . . 64-Kword Block 1F0000 . . . 01FFFF 64-Kword Block 010000 00FFFF 64-Kword Block 000000 Word Mode (x16) 4 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... Enabled Enabled Enabled X X VIL VIL X X VIH VIH X X See See Figure 2 Table High Z High Z Note 6 Note 7 5 MX26L6419 Read Read Write Status Status (WSM off) (WSM on) 8,9 VIH VIH VIH Enabled Enabled VIL VIL VIH VIH VIH VIL ...
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... WE is active and high level. Address and data are latched on the earlier rising edge of WE and CE. Standard micro-processor write tim- ings are used. P/N:PM0946 MX26L6419 OUTPUT DISABLE When VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. STANDBY When CE disable the device (see table1) and place it in standby mode ...
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... Protection Lock-Bit Sector Program Lock-Bit Write Write Write 60H 60H C0H Write Write Write 01H D0H PD 7 MX26L6419 Write to Word Sector Buffer Program Erase 7,8,9 10,11 9,10 > Write Write Write E8H 40H/10H 20H Write Write Write ...
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... The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 10.Attempts to issue a block erase or program to a locked block. 11.Either 40H or 10H are recognized by the WSM as the word program setup. 12.The clear block lock-bits operation simultaneously clears all block lock-bits. P/N:PM0946 MX26L6419 8 REV. 0.3, OCT. 08, 2003 ...
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... Reserved for Future Implementation Block 31 Lock Configuration Reserved for Future Implementation (Block 2 through 30) Block 1 Reserved for Future Implementation Block 1 Lock Configuration Reserved for Future Implementation Block 0 Reserved for Future Implementation Block 0 Lock Configuration Device Code Manufacturer Code 9 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... ASCII "Q" in the low byte (DQ 0-7 ) and 00h in the high byte (DQ 8- Query addresses containing two or more bytes of in- formation, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. P/N:PM0946 MX26L6419 10 REV. 0.3, OCT. 08, 2003 ...
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... PrVendor 23h ID# 24h PrVendor 25h TblAdr 26h AltVendor 27h ID# 28h ... ... 11 MX26L6419 Query data with byte addressing Hex Hex ASCII Offset Code Value 20: 51 "Q" 21: 00 "Null" 22: 52 "R" 20: 51 "Q" ...
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... Unlocked 1 = Locked BSR 1-7: Reserved for Future Use NOTE The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word mode). P/N:PM0946 MX26L6419 Name Description Manufacturer Code Device Code Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset ...
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... P/N:PM0946 MX26L6419 Add. 10 11: 12: 13: 14: 15: 16: 17: 18: ...
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... Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) 2Dh 4 Erase Block Region 1 Information bits 0- y+1 = number of identical-size erase blocks bits 16- region erase block(s) size are z x 256 bytes P/N:PM0946 MX26L6419 n in number of bytes n 14 Code See Table Below 27: ...
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... BCD value in volts (P+D)h 1 VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0". P/N:PM0946 MX26L6419 Add. 31: 32: 33: 34: 35: 36: 37: ...
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... Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+15)h Reserved for future use NOTE: 1. The variable pointer which is defined at CFI offset 15h. P/N:PM0946 MX26L6419 n = factory pre-programmed bytes n = user-programmable bytes n HEX value represents the number 16 Add. Hex ...
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... This mode is func- tional over the entire temperature range of the device. To activate this mode, the two cycle "Silicon ID Read" command is requested. (The ID code value is illustrated in Table 13.) Table 13. MX26L6419 Silicon ID Codes Type Manufacture Code Device Code Block Lock Configuration ...
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... Yes RESERVED XSR.0 Notes: 1. After a Buffer-Write command, XSR indicates that a Write Buffer is available. 2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register. P/N:PM0946 MX26L6419 Definition "1" "0" Ready Busy Error in Block Erasure or Successful Block ...
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... Block Address (see Figure 4, Write to Buffer Flowchart on page 25). After the com- mand is issued, the extended Status Register (XSR) can P/N:PM0946 MX26L6419 be read when CE is VIL. XSR.7 indicates if the Write Buffer is available. If the buffer is available, the number of words to be pro- gram is written to the device ...
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... ACC pin may be connected to 12V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. P/N:PM0946 MX26L6419 20 REV. 0.3, OCT. 08, 2003 ...
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... R 15(A15 RCR.15 = READ MODE (RM Standard Word Reads Enabled (Default Page-Mode Reads Enabled RCR.14-0= RESERVED FOR FUTURE ENHANCEMENTS (R) P/N:PM0946 MX26L6419 Notes Read mode configuration effects reads from the MTP array. Status register, query, and identifier reads support standard word read cycles ...
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... The device is switched to this mode by writing the Read Identifier command 90H. Once in this mode, read cycles from addresses retrieve the specified informa- P/N:PM0946 MX26L6419 tion. To return to read array mode, write the Read Array command (FFH). Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command ...
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... VPEN must be kept at or below VCC during VPEN transitions. Figure 3. Protection Register Memory Map Address NOTE: The lowest order address line is A0. P/N:PM0946 Word A[21 - 0]: 64 Mbit 88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 1 Word Lock 80H 23 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... A21- P/N:PM0946 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... Write Word Count - Address=Any address in block - Data=word count - Valid range=0x0 thru 0x1F Confirm Cycle - Issue Confirm Command - Address=Any address in block - Data=0xD0 Read Status Register See Status Register Flowchart YES Error-Handler Any Errors? User-defined routine NO End 25 MX26L6419 NO Write to Buffer Time-Out ? YES REV. 0.3, OCT. 08, 2003 ...
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... See Suspend/Resume Flowchart Program Suspend SR2 = '1' See Suspend/Resume Flowchart SR5 = '1' SR4 = ' Error Erase Failure Y es Error SR4 = '1' Program Failure Error SR3 = '1' V < V PEN PENLK Error SR1 = '1' Block Locked No End 26 MX26L6419 Error Command Sequence REV. 0.3, OCT. 08, 2003 ...
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... SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register Command in cases where multiple lo- cation are programmed before full status is checked error is detected, clear the status register before attempting retry or other error recovery. 27 MX26L6419 Comments Data=40H Programmed Data=Data to Be Programmed Addr=Location to Be ...
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... Figure 7. Block Erase Flowchart Write 20H to Block Address Write Confirm D0H to Block Address P/N:PM0946 Start Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Erase MTP Block(s) Completed 28 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... Write 01H, Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR.4,5=1 ? Command Sequence Error NO NO Set Lock-Bit Error SR.4=0 ? YES Set Lock-Bit Successful 29 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... Write D0H Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed Read Status Register Data (See Above) NO Voltage Range Error SR.3=0 ? YES YES SR.4,5=1 ? Command Sequence Error NO NO SR.5=0 ? Clear Block Lock-Bits Error YES Clear Block Lock-Bit Successful 30 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Program Completed Read Status Register Data (See Above) 1,1 VPEN Range Error SR.3, SR.4= 0,1 Protection Register SR.1, SR.4= Programming Error 1,1 Attempted Program to Locked SR.1, SR.4= Register-Aborted YES Program Successful 31 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... OPERATING RATINGS Commercial (C) Devices +150 o C Ambient Temperature (T V Supply Voltages CC V for full voltage range +3 3 +125 C CC Operating ranges define those limits between which the functionality of the device is guaranteed. 32 MX26L6419 ). . . . . . . . . . . . 0° +70°C A REV. 0.3, OCT. 08, 2003 ...
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... Device is enabled (see Table 1) 2 f=5MHz, IOUT=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Max Device is enabled (see Table 1) f=33MHz, IOUT=0mA CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC 33 MX26L6419 REV. 0.3, OCT. 08, 2003 ...
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... VLKO (min) and VCC (min), and above VCC (max). P/N:PM0946 Notes Min Max Unit 2 -0.5 0 2.0 VCCQ+0 0 VCCQ 2 VCCQ-0.2 V 0.5xVCC V 3,4 3 MX26L6419 Test Conditions VCCQ=VCCQ2/3 Min IOL=2mA VCCQ=VCCQ2/3 Min IOL=100uA VCCQ=VCCQ Min IOH=-2.5mA VCCQ=VCCQ Min IOH=-100uA REV. 0.3, OCT. 08, 2003 ...
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... Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ). Input rise and fall times (10% tp 90%)<5ns. Figure 12. Transient Equivalent Testing Load Circuit Device Under Test NOTE: CL Includes Jig Capacitance Test Configuration C L (pF) VCCQ = VCC = 3.0 V-3 P/N:PM0946 MX26L6419 VCCQ/2 Output TEST POINTS 1.3V 1N914 RL=3.3K ohm Out CL 35 REV. 0.3, OCT. 08, 2003 ...
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... When reading the MTP array a faster tGLQV (R15) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word read mode, R14 (tAPA) will equal R1 (tAVQV). P/N:PM0946 MX26L6419 VCC 3.0V-3.6V(3) VCCQ 3.0V-3.6V(3) Notes ...
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... P/N:PM0946 tAVAV Valid Address Valid Address Valid Address tAVQV tELQV tGLQV tAPA tELQX Valid Valid Valid Output Output Output tGLQX X 37 MX26L6419 Valid Address tEHEL tEHQZ tGHQZ tOH High Z Valid Output high is defined at the first edge of CE that REV. 0.3, OCT. 08, 2003 ...
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... Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL . 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5=0). P/N:PM0946 MX26L6419 Valid for All Speeds Notes Min ...
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... Write block erase or write buffer confirm, or valid address and data. d. Automated erase delay. e. Read status register or query data. f. Write Read Array command. P/N:PM0946 AIN AIN tWHAX (tEHAX) tWHGL (tEHGL) tWHEH (tEHWH) tWPH tWHDX (tEHDX) DIN DIN tVPWH (tVPEH) 39 MX26L6419 E F Valid DIN SRD tQVVL REV. 0.3, OCT. 08, 2003 ...
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... NOTES: 1. These specifications are valid for all product versions (packages and speeds RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RESET Pulse Low Time is 100ns. P/N:PM0946 tPLPH 40 MX26L6419 Notes Min Max Unit REV ...
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... Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25° C, f=1.0MHz DATA RETENTION Parameter Minimum Pattern Data Retention Time P/N:PM0946 MX26L6419 LIMITS MIN. TYP.(2) 2.0 218 210 0.8 100 MIN. -1.0V -1.0V -1.0V -100mA Test Set ...
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... ORDERING INFORMATION PLASTIC PACKAGE Part NO. MX26L6419TC-10 P/N:PM0946 Access Time Package type (ns) 100/25 48-TSOP 42 MX26L6419 Cycles 100 REV. 0.3, OCT. 08, 2003 ...
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... PACKAGE INFORMATION P/N:PM0946 MX26L6419 43 REV. 0.3, OCT. 08, 2003 ...
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... Input max. voltage with respect to GND on OE from 13.5V to 12.5V b. Input max. voltage with respect to GND on power, address, CE, WE from 13.5V to 2xVCC max. c. test condition from VCC=5.0V to VCC=3V Capacitance: a. CIN from 8pF(max.) to 7.5pF(max.) b. COUT from 8pF(typ) to 8.5pF(typ) c. Add CIN2 P/N:PM0946 MX26L6419 Page P44 P1,2,5,6,10 P34,6 P39 P1,13,20,33, 35,36,37,42 P34 ...
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... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. MX26L6419 ...