SC220 ZARLINK [Zarlink Semiconductor Inc], SC220 Datasheet
SC220
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SC220 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... BUFFER 32 MEMORY XpressFlow BUS XpressFlow BUS SC220 - XpressFlow Engine General Description The XpressFlow Engine contains the switching data base in- terface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management ...
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... CAM MAPPING Interface TABLE 16 16 SRAM Control CONTROL Buffer 32 BUFFER Memory MEMORY 32 Interface 32 Block Diagram – SC220 XpressFlow Engine Typical Application : A 16-port Ethernet Switch with 4-Fast Ethernet Address Mapping Table SC220 XpressFlow Engine Buffer RAM Buffer Buffer EA208E RAM RAM 8-Port ...
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... P_CLK for meeting the 80386 timing requirement. The RSTOUT pin for SC220 has a totally different function longer related with the RSTIN input. The RSTOUT is a watch- dog output from SC220 to keep track of the active state of the host processor. Host processor needs to access the Keep Alive register periodically to prevent the setting of the RSTOUT output ...
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... CMOS I/O-OD XpressFlow Bus – High Priority Request CMOS Input ** XpressFlow Bus – Bus Request [8:1] CMOS Output XpressFlow Bus – Bus Grant [8:1] CMOS Output XpressFlow Bus – Bus Overload CMOS Input XpressFlow Bus – Clock SC220 XpressFlow Engine or Rev. 4.5 – February ...
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... CMOS Output Local Memory Bus- Read Chip Select [2:0] CMOS Output Local Memory Bus – Write Chip Select [3:0] [3:0] CMOS Output Local Memory Bus – Controller Address Status CMOS Output Local Memory Bus – Synchronous Clock SC220 XpressFlow Engine Rev. 4.5 – February ...
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... Reserved Pins (5 pins) Input +3.3 Volt DC Supply for Core Logic (6 pins) Input +3.3 Volt DC Supply for I/O Pads (23 pins) Input Ground for Core Logic (6 pins) Input Ground for I/O Pads (26 pins SC220 XpressFlow Engine Rev. 4.5 – February ...
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... Vertex Networks, Inc. 1999 CAM Interface XpressFlow Bus Interface SC220 XpressFlow Engine 193 192 P_INT P_RWC P_RSTOUT P_RSTIN# VSS P_CLK VDD P_D[31] P_D[30] P_D[29] P_D[28] VSS P_D[27] P_D[26] VDD P_D[24] P_D[25] ...
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... S_D S_D [5] [8] [11] [14] [17] [19] [22] S_D S_D S_D S_D S_D S_D S_D [6] [9] [12] [15] [16] [18] [21 SC220 XpressFlow Engine C_D P_A P_A P_A P_A P_ P_ [13] [11] [8] [6] [3] BS16# RDY# C_D P_A P_A P_A P_ P_A P_ [14] ...
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... VSS S_GNT[1]# 189 P_RSTIN# S_REQ[2]# 190 P_RSTOUT VSS 191 P_RWC S_GNT[2]# 192 P_INT SC220 XpressFlow Engine Pin No. Signal Name 193 P_RDY# 194 P_BS16# 195 P_CS# 196 P_ADS# 197 VDD 198 P_A[1] 199 P_A[2] 200 VSS 201 P_A[3] ...
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... For 256-BGA package: E4, G4, L4, N4, T4, U6, U8, U11, U13, W14, T17, M17, K17, H17, E17, D16, D13, D10, D9, D7, and D5 are VSS. © 1998 Vertex Networks, Inc. 1999 SC220 XpressFlow Engine Rev. 4.5 – February ...
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... Vertex Networks, Inc. 1999 CAM Block Diagram – CAM Interface SC220 XpressFlow Engine Command From HISC Block Response To HISC Data Block CAM Interface Logic Command From CPU Block Response To CPU Data Block Rev. 4.5 – February ...
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... Note: Refer to MUSIC MU9C1480 CAM data sheet for detailed timing parameters. © 1998 Vertex Networks, Inc. 1999 Write MAC Address Byte 4, & SC220 XpressFlow Engine Read MAC Control Buffer Pointer Rev. 4.5 – February ...
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... Local Memory Controller Address Status – to load a new address. Output L_CLK CMOS Local Memory Clock – a synchronous clock to memory devices. Output © 1998 Vertex Networks, Inc. 1999 SC220 XpressFlow Engine Rev. 4.5 – February ...
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... A3 A3+1 A3+2 A3+3 A4 A4+1 A4+2 D3 D3+1 D3+2 D3 SC220 XpressFlow Engine Chip #1 Chip #0 ---- ---- L_WE[0]# L_OE[0]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# ---- ---- L_WE[0]# L_OE[0]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# ---- ---- L_WE[0]# L_OE[0]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# A4 D4+1 D4+2 D4+3 D5 Rev. 4.5 – February ...
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... Hi 2x Clock Big Endian C[1]=Low P_R/W# is used for PowerPC or other similar processors. C[1]=High P_W/R# is used for 386, 486 or other similar processors SC220 XpressFlow Engine C[2] C[3] C[4] RWC Bus Width RDY Timing P_R/W# 16-bit Normal P_W/R# 32-bit Early Rev. 4.5 – February ...
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... Typical Motorola MPC801 CPU I/O Access Operations 2.3.3 Intel 486 Processor Interface P_CLK P_ADS# P_A[11:1] P_CS# P_W/R# P_RDY# P_D[31:0] (in) P_D[31:0] (out) Typical 486 CPU I/O Access Operations © 1998 Vertex Networks, Inc. 1999 SC220 XpressFlow Engine Rev. 4.5 – February ...
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... P_RSTIN# P_RSTOUT# Internal PH2 Clock Synchronization Note: See Intel 386 Processor Data Book for more details © 1998 Vertex Networks, Inc. 1999 PH2 PH2 or PH1 SC220 XpressFlow Engine PH1 PH2 Rev. 4.5 – February ...
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... SC220 XpressFlow Engine Big Reg. W/R Note: Endian Size hF02 16-bit W/-- hF02 16-bit --/R hF12 16-bit --/R hF22 16-bit W/R hF32 16-bit W/R hF42 16-bit ...
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... D-word hA98 nd D-word hAA8 rd D-word hAB8 h908 h928 h938 h980 h998 h9B0 SC220 XpressFlow Engine Big Reg. W/R Note: Endian Size hC02 16-bit W/R hC22 16-bit --/R hC32 16-bit --/R hC82 16-bit W/R hC92 16-bit W/R hCA2 16-bit W/R hCB2 ...
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... Built-in intelligent bus load regulator for data traffic balancing t Provides centralized bus arbitration with two level request priorities High priority for Data Messages Low priority for Command Messages Processor Interface Configuration bit [0: SC220 XpressFlow Engine Rev. 4.5 – February ...
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... High Priority Request pre-empts the low priority request © 1998 Vertex Networks, Inc. 1999 Data Xfer w/o Data Other XpressFlow Bus Cycles SC220 XpressFlow Engine D5 EoF EOF C0 C1 Aborted Command Rev. 4.5 – February ...
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... Test Mode Selection & Test Output – Set Test Mode upon Reset, I/O and provides test status output during test mode © 1998 Vertex Networks, Inc. 1999 XpressFlow Bus arbitration SC220 XpressFlow Engine Rev. 4.5 – February ...
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... -1 VDD x 70% -0.5 2.0 -0.3 2.0 -0 OUT = SC220 XpressFlow Engine Preliminary Typ Max Unit 40.0000 MHz 50.0000 MHz 66.6666 MHz 300 500 mA 300 500 mA 300 500 VDD ...
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... Output float delay timing S_CLK S_D[31:0] S_MSGEN# S_EOF# S_IRDY S_TABT# S_HPREQ# S_REQ[7:0]# XpressFlow Bus Interface – Input setup and hold timing SC220 XpressFlow Engine S12 S1-min S13 S2-min S14 S3-min S15 S4-min S17 S18 S19 S20 S21 S22 S23 S24 ...
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... SC220 XpressFlow Engine -66 Max Min (ns) Max Note: (ns) (ns 8 50pf 8 50pf 8 50pf 8 50pf 8 50pf 8 50pf 8 20pf ...
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... Max Min (ns) (ns) (ns 3.5 2 3.5 2 3.5 2 3.5 2 3.5 2 3 SC220 XpressFlow Engine P10 P11 P12 CPU Bus Interface – -66 Max Min Max Note: (ns) (ns) (ns ...
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... SC220 XpressFlow Engine L3-max L3-min L4-max L4-min L5-max L5-min L6-max L6-min L7-max L7-min L8-max L8-min L9-max L9-min -66 Min Max Note: (ns) (ns 30pf ...
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... SC220 XpressFlow Engine C7-max C7-min C8-max C8-min C9-max C9-min C10-max C10--min C11-max C11-min -66 Min Max Note: (ns) (ns Rev. 4.5 – ...
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... PQFP 256 1 Pin 1 I. 0.40 TYP 3.40 4.10 ± 0.20 MAX. 0.25 MIN. © 1998 Vertex Networks, Inc. 1999 30.6 ± 0.20 25.2 REF 193 128 D 0.14/0.22 28.0 ± 0.20 C 1.30 REF. 0.50/0. SC220 XpressFlow Engine 192 25.2 28.0 30.6 B REF ± 0.20 ± 0.20 129 Rev. 4.5 – February ...
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... Irvine, CA 92606-4950 Tel. 1-714-252-8880, FAX: 1-714-252-8868 Web Site: www.vertex-networks.com 0.50 / 0.70 Identification Industrial B = BGA SC220 XpressFlow Engine 1.27 C Vertex Networks Use Revision TAV rrr Revision - 001 = Rev ...
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CONTROLLING DIMENSIONS ARE DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...