hd66421 Renesas Electronics Corporation., hd66421 Datasheet
hd66421
Related parts for hd66421
hd66421 Summary of contents
Page 1
... Die with gold bump This function realize low power consumption because high voltage for driving LCD is not needed. An MPU can access HD66421 at any time, because the MPU operations are asynchronous with the HD66421's system clock and display operation. Its low-voltage operation at 2.2 to 5.5V and ...
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... RES VCC4 GND4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCC5 GND5 VCC6 VLCD4 GND6 Note: This figure is not drawn to a scale COM100 COM99 COM98 COM51 SEG160 SEG159 SEG158 SEG3 SEG2 SEG1 COM50 COM49 COM3 COM2 COM1 2 HD66421 ...
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... SEG5 -4217 -998 56 SEG6 -4217 -1049 57 SEG7 -4217 -1099 58 SEG8 -4217 -1149 59 SEG9 -4217 -1199 60 SEG10 -4217 -1249 3 Rev. 1.1E '99.02.10 HD66421 GND1 COM100 SEG137 dummy8 No. PAD NAME SEG11 -4217 -1299 62 SEG12 -4217 -1349 63 SEG13 -4217 -1399 64 SEG14 -4217 -1449 65 SEG15 ...
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... SEG129 2472 -2082 187 SEG130 2522 -2082 188 SEG131 2572 -2082 189 SEG132 2622 -2082 190 SEG133 2672 -2082 4 HD66421 No. PAD NAME X Y 191 SEG134 2722 -2082 192 SEG135 2772 -2082 193 SEG136 2822 -2082 194 dummy 7 3419 -2075 195 ...
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... RD -1407 2195 306 -1487 2195 Vcc4 -1587 2195 307 -1667 2195 -1770 2195 308 GND5 -1850 2195 5 Rev. 1.1E '99.02.10 HD66421 No. PAD NAME X Y 309 DB0 -1948 2195 -2028 2195 310 DB1 -2131 2195 -2211 2195 311 DB2 -2310 2195 -2390 ...
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... GND Description Vcc: +2.2V to +5.5V, GND: 0V Power supply to LCD driving circuit Several levels of power to the LCD driving outputs. Master HD66421 outputs these levels to the slave HD66421. Must be connected to external resister when using R-C oscillation. When using an external clock, it must be input to the OSC terminal. Clock output ...
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... W BK8 BK9 BK10 BK11 BK12 BK13 BK14 BK15 HD66421 Data bits IR4 IR3 IR2 IR1 DTY1 DTY0 INC GRAY XA5 XA4 XA3 XA2 XA1 XA0 ST5 ST4 ST3 ST2 ST1 BK16 BK17 BK18 BK19 ...
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... GRAY = 0: Grayscale palette is not available(4-gray scales fixed) DTY1, 0 DTY1 (1,1): 1/8 display duty cycle - Partial display DTY1 (1,0): 1/64 display duty cycle DTY1 (0,1): 1/80 display duty cycle DTY1 (0,0): 1/100 display duty cycle INC INC = 1: X address is incremented for each access INC = 0: Y address is incremented for each access 8 Rev. 1.1E '99.02.10 HD66421 ...
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... DSEL = 1: Plane 1 is displayed DSEL = 0: Plane 0 is displayed PSEL PSEL = 1: Plane 1 is read/written from the MPU PSEL = 0: Plane 0 is read/written from the MPU CLE CLE = 1: CO,CL1,FLM,M stop in master mode. They are high-Z. CLE = 0: CO,CL1,FLM,M are operating in master mode. Normal operation. 9 Rev. 1.1E '99.02.10 HD66421 ...
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... Grey scale Data Buffer palette MPX I/O control V3O V5O FLM M CL1 VLCD V2O V4O 5 10 Rev. 1.1E '99.02.10 HD66421 COM100 Comparator Row Decoder Counter Display Line Counter Grey scale pattern Generator Timing Generator Oscillator DCON OSC OSC2 RES ...
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... Preliminary System Description The HD66421 can display a maximum of 160 x 100 dots (ten 16x16-dot characters x 6 lines) four-level gray scale or four colour LCD panel. Four levels of gray scale can be selected from 32-levels, so the appropriate 4-level gray scale can be displayed. And Monochrome display can be selected from two planes ...
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... Preliminary MPU Interface The HD66421 can interface directly to an MPU through an 8-bit data bus or through an I/O port (figure 2). The MPU can access the HD66421 internal registers independently of internal clock timing. The index register can be directly accessed but the A15 - A0 Z80 H8/325 ...
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... Preliminary LCD Driver Configuration Row and column outputs: The HD66421's row outputs is only both sides. In any case, each output's function is fixed; COM1 to COM100 output row signals and SEG1 to SEG160 output column signals. Row outputs from both sides of LCD 50-channel row output ...
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... Preliminary Column Address Inversion According to LCD Driver Layout: The HD66421 can always display data in address H'0 on the top left of an LCD panel regardless of where it is positioned with respect to the panel. This is because the HD66421 can invert the positional relationship between display RAM addresses and LCD driver output pins by inverting RAM addresses ...
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... levels are supplied from the master LSI. If the internal power supply circuit can not drive two LSIs, use an external power supply circuit. Figure 6 shows the configuration using two HD66421s and table 2 lists the differences between master and slave modes. Dot-matrix Display 320 x 100 V1O to ...
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... Preliminary Display RAM Configuration and Display The HD66421 incorporates a bit-mapped display RAM. It has 320 bits in the X direction and 100 bits in the Y direction. The 320 bits are divided into forty 8-bit groups. As shown in figure 7, data written by the MPU is stored horizontally with the MSB at the far left and the LSB at the far right ...
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... MON = 1, ADC = 0 Figure 10 Display RAM Configuration in Monochrome Mode LCD panel Display RAM (b) MON = 1, ADC = 1, WLS= 0 SEG1 LCD drive signal output SEG160 H'00 H'01 H'62 H'63 H'26 H'24 H'26 MSB (b) MON = 1, ADC = 1 17 HD66421 ...
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... Preliminary Word Length The HD66421 can handle either 8- or 6-bits as a word. In the display memory, one X address is assigned to each word 6-bits long in X direction. LCD drive signal output SEG1 H'00 H'01 8 bits H'62 H'63 H'0 H'1 X addresses MSB (a) Address assignment when one word is 8 bits long (MON=0) ...
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... Preliminary Monochrome Display Mode The HD66421 can control monochrome display. This mode is set when MON is set to 1. Two plane of display can be selected in this mode using two bits data for gray scale. One plane can be selected with PSEL bit for access from the CPU and with DSEL bit for display ...
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... Packed Pixel Method For grey scale display and super reflective colour display, multiple bits are needed for one pixel. In the HD66421, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour display. One address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as consecutive bits in one byte ...
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... Table 5 Grayscale Levels (GRAY= 1) DB7,5,3,1 DB6,4,2 Grayscale Level default R12 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 default R13 11/31 12/31 13/31 14/31 15/31 16/31 17/31 18/31 19/31 20/31 21/31 22/31 default R14 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 default R15 1 Grayscale Level 0 0 1 HD66421 ...
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... RAM, first write the RAM address desired to the X address register (R2) and the Y address register (R3). Then read/write the display memory access register (R4). Memory access by the MPU is independent of memory read by the HD66421 and is also asynchronous with the HD66421's clock, thus enabling an interface independent of HD66421's internal operations ...
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... Preliminary Display RAM Reading by LCD Controller: Data is read by the HD66421 to be displayed asynchronously with accesses by the MPU. However, because simultaneous access could damaging data in the display RAM, the HD66421 internally arbitrates access timing; access by the H'0 H'1 H'00 H'01 Valid area H'63 Invalid area H'7F WLS= 0 H'0 H'1 H'00 H'01 H'02 H'63 WLS= 0 ...
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... Figure 18 The Flow Chart for Read-Modify-Write Y-address is address without re-setting the address. Data is temporarily latched into a HD66421's buffer and then output next time a read is performed in a subsequent cycle. This means that the dummy read is necessary after every cycle. This sequence is shown in figure 18. ...
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... Preliminary Arbitration Control The HD66421 controls the arbitration between draw access and display access. The draw access read and write display data memory incorporated in the HD66421. The display access outputs display data to the liquid crystal panel. The draw access has the priority over display access, so continuous access is enabled without having the system to wait ...
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... Preliminary Vertical Scroll Function The HD66421 can vertically scroll a display by varying the top raster to be displayed. which is specified by the display start raster register. Figure 22 and 23 show vertical scroll examples. As shown, when the top raster to be displayed is set to Top raster to be displayed = 0 ...
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... Preliminary Y-address H'00 H'01 H'02 H'03 H'04 Top raster to be H'05 displayed = 0 H'06 H'07 H'08 H'09 H'0A H'4C H'4D H'4E H'4F Y-address H'01 H'02 H'03 H'04 Top raster to be H'05 displayed = 1 H'06 H'07 H'08 H'09 H'0A H'0B H'4D H'4E H'4F H'50 Y-address H'02 H'03 H'04 H'05 H'06 H'07 H'08 Top raster to be H'09 displayed = 2 H'0A H'0B H'0C H'4E H'4F H'50 H'51 Figure 23 Vertical Scroll : 1/80Duty Cycle 27 HD66421 ...
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... Preliminary Partial Display Function The HD66421 can display only a part of a full display. The duty ratio of this partial display is 1/8 and rest of display is scanned with unselected levels. The position of this partial display can be located at any position with using partial display position register. To launch this mode, following ...
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... Preliminary Blink Function The HD66421 can blink a specified area on the dot-matrix display. Blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. For example, when frequency is 80 Hz. the area is turned on and off every 0.8 seconds. The area to be blinked can be designated by specifying vertical and horizontal positions of the area ...
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... The HD66421 has a standby function providing low power-dissipation, which is initiated by internal register settings. During standby mode, all the HD66421 functions are inactive and data in the display RAM and internal registers except the DISP bit are retained. However, only control registers can be accessed during standby mode. ...
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... Set DISP bit to 1 (control register 1) Clear DISP bit to 0 (control register 1) Clear PWR,AMP bit to 0 (control register 1) Figure 29 Procedure for Turning Power Supply On/Off strictly followed to prevent incorrect display because the HD66421 incorporates a power supply circuit. Turn off power 31 Rev. 1.1E '99.02.10 ...
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... Preliminary Oscillator The HD66421 incorporates two sets of R-C oscillator for two display modes: OSC-OSC1 oscillator is used for 32-levels gray scale display mode and OSC-OSC2 oscillator for 4-levels gray scale display mode. If the internal oscillator is not used, an appropriate clock signal must be externally input through the OSC pin ...
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... LCD, a 6-level power supply are necessary. These levels are generated internally or supplied from outside. When an internal voltage levels generator is chosen, external capacitors are needed to stabilize these levels. AS the HD66421 incorporates operational amplifiers to these levels, this circuit gives better quality of display with less power consumption ...
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... Preliminary LCD drive levels bias ratio: LCD driving levels bias ratio can be selected from 1/8, 1/9, 1/10 or 1/11. Power Supply: The HD66421 needs the external power supply for LCD driving circuit. If this power circuit has on/off control, the HD66421 controls the external power supply circuit by setting PWR bit ...
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... Note that if the reset conditions specified in the Electric Characteristics section are not satisfied, the HD66421 will not be correctly initialized. In this case, the internal registers of the HD66421 must be initialized by software. Initial Setting of Internal Registers: All the internal register bits are cleared to 0. Details are listed below ...
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... Preliminary Internal Registers The HD66421 has one index register and 18 data registers, all of which can asynchronously with the internal clock. All the registers except the display memory access register are write-only. Accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to. ...
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... Preliminary Control Register 2 (R1): Control register 2 (figure 34) controls general operations of the HD66421. Each bit has its own function as described below. BIS1, BIS0 bits BIS1 (1, 1): 1/8 LCD drive levels bias ratio BIS1 (1, 0): 1/9 LCD drive levels bias ratio BIS1 (0, 1): 1/10 LCD drive levels bias ratio ...
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... ST6 ST5 ST4 ST3 BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0 BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0 38 Rev. 1.1E '99.02.10 HD66421 ST2 ST1 ST0 ...
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... COM68 to COM61 H'0B COM60 to COM53 GP14 GP13 GP12 GP11 GP10 GP24 GP23 GP22 GP21 GP20 GP34 GP33 GP32 GP31 GP30 GP44 GP43 GP42 GP41 GP40 39 Rev. 1.1E '99.02.10 HD66421 1 0 BK6 BK7 1 0 PB1 PB0 (ADC= "0". If "1" , reverse direction ...
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... Alternative Cycle Frame 7 lines 11 lines 13 lines CC3 CC2 CM1 CM0 CC4 40 Rev. 1.1E '99.02.10 HD66421 alternative drive cycle register Gray scale Level 16/ 17/ 18/31 0 19/ 20/ 21/ 22/ ...
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... LCD panel. This linearity will be lost if LCD panel is connected. In this case, the four appropriate levels must be selected from grayscale No.1 to 31. 2.4 2.3 2.2 R14(Default) R13(Default) 2.1 2 Figure 45 LCD Effective Value VLCD=15V, Ta=25˚C, 1/9 bias LSI (No load) LSI + LCDpanel Grayscale No. 41 HD66421 ...
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... Preliminary Plane Selection Register (R17): The plane selection register (figure 46) controls general operations of the HD66421. Each bit has its own function as described below. MON bit MON = l: Monochrome display MON = 0: 4-level gray scale display Data bit Set value Figure 46 Plane Selection Register (R17) ...
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... If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics to prevent malfunction or unreliability. Symbol Ratings Vcc -0.3 to +7.0 VLCD -0.3 to +20.0 VT1 -0.3 to Vcc+0.3 VT2 -0.3 to VLCD+0.3 Topr -40 to +85 -55 to +110 Tstg 43 Rev. 1.1E '99.02.10 HD66421 Unit Notes °C °C ...
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... Typ Max Unit - µA - µ 0.8xVcc - Vcc 0.2xVcc V 0.8xVcc - Vcc 0.2xVcc V - T.B.D µ µ T.B.D µA 44 HD66421 Measurement Condition Notes Vin=Vcc to GND 1 Vin=GND to VLCD 2 Ion = 100µA 3 VLCD = IoH=-50µA 4 IoL=50µA 4 Vcc = 3. 180k ...
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... Preliminary Input Terminal Pins: CS, RS, WR, RD, RES, M/S Pins: DB7 to DB0, FLM, M, CL1 I/O Terminal Input Enable Figure 47 Terminal Configuration Output Terminal Pins Rev. 1.1E '99.02.10 HD66421 M/S CO data Output Enable Data ...
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... DHW Symbol Min Typ Max t 1 – – RES t WRDH t WWRH DHR Figure 44 MPU Interface 30pF(includes board capacitance) 46 Rev. 1.1E '99.02.10 HD66421 ) Note 1 Unit Notes kHz Rf = 180k , Vcc = 3.0V kHz % µ s µ s Unit Notes ns Vcc = 2.2V to 3.0V Vcc = 3.0V to 5.5V, 2 – Vcc = 2.2V to 3.0V Vcc = 3.0V to 5.5V, 2 – ...