mx25l12845e Macronix International Co., mx25l12845e Datasheet - Page 7

• Manufacturer Part Number: mx25l12845e
• Description: Mx25l12845e High Performance Serial Flash Specification Preliminary
• Manufacturer: Macronix International Co.

P/N: PM1428
GENERAL DESCRIPTION
MX25L12845E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it
is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12845E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25L12845E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the per-
formance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L12845E, MXSMIO
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device.
It features 8 bit input/output for increasing throughputs. This feature is recommeded to be used for factory produc-
tion purpose.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L12845E utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
MX25L12845E
Part Name
Part Name
MX25L12845E
Additional
Additional
Featu-
Featu-
res
res
Individual block
Flexible or
(or sector)
(command :
protection
Protection and Security
AB hex)
17 (hex)
RES
V
secured OTP
(command :
4k-bit
C2 17 (hex)
(if ADD=0)
REMS
90 hex)
V
TM
(Serial Multi I/O) flash memory, provides sequential read operation on whole chip and
(104MHz)
1 I/O
Read
V
(command :
C2 17 (hex)
(if ADD=0)
REMS2
EF hex)
(70MHz)
2 I/O
Read
V
Identifier
(70MHz)
4 I/O
Read
V
C2 17 (hex)
(command :
(if ADD=0)
REMS4
DF hex)
Performance
DT Read
(50MHz)
1 I/O
Read
V
7
DT Read
(50MHz)
C2 17 (hex)
(command :
(if ADD=0)
2 I/O
REMS4D
CF hex)
V
DT Read
(50MHz)
4 I/O
V
C2 20 18 (hex)
(command:
9F hex)
Parallel Mode
RDID
(6MHz)
8 I/O
MX25L12845E
V
REV. 0.06, MAR. 05, 2009